git.libre-soc.org Git - soc.git/history - src/soc/simple/core

2021-12-15	Luke Kenneth Casso...	sort out MSR, read/write in same way as PC/SVSTATE...	blob \| commitdiff \| raw
2021-11-22	Luke Kenneth Casso...	make FetchFSM take PC as an input in its ispec	blob \| commitdiff \| raw \| diff to current
2021-11-21	Luke Kenneth Casso...	fixed issue with hazard dependencies, read will nott	blob \| commitdiff \| raw \| diff to current
2021-11-19	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2021-11-18	Luke Kenneth Casso...	set up a temporary copy of CoreInput	blob \| commitdiff \| raw \| diff to current
2021-11-17	Luke Kenneth Casso...	add a FetchOutput pipeline data structure	blob \| commitdiff \| raw \| diff to current
2021-11-11	Luke Kenneth Casso...	split out core input/output into separate file core_data.py	blob \| commitdiff \| raw \| diff to current