git.libre-soc.org Git - soc.git/history - src/soc/simple/test/test

[soc.git] / src / soc / simple / test / test_runner.py

2021-03-30	Alain D D Williams	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw
2021-03-30	Luke Kenneth Casso...	use port name for INT regfile to match up with test_run...	blob \| commitdiff \| raw
2021-03-30	Cesar Strauss	Memory port seems to have been renamed	blob \| commitdiff \| raw \| diff to current
2021-03-28	Luke Kenneth Casso...	rather invasive reduction of SPR regfile size	blob \| commitdiff \| raw \| diff to current
2021-03-28	Luke Kenneth Casso...	reduce number of regfile ports	blob \| commitdiff \| raw \| diff to current
2021-03-22	Cesar Strauss	Add traces for the new FSM and integer predicate decoding	blob \| commitdiff \| raw \| diff to current
2021-03-09	Cesar Strauss	Add some extra debug traces to the GTKWave document	blob \| commitdiff \| raw \| diff to current
2021-03-09	Cesar Strauss	Create a new signal for the Simulator to wait on	blob \| commitdiff \| raw \| diff to current
2021-03-08	Luke Kenneth Casso...	add option in TestRunner to disable svp64 via commandli...	blob \| commitdiff \| raw \| diff to current
2021-03-03	Luke Kenneth Casso...	set SVSTATE in TestRunner using new TestIssuer.svstate_i	blob \| commitdiff \| raw \| diff to current
2021-03-03	Luke Kenneth Casso...	add svstate_i to TestIssuer which mirrors pc_i	blob \| commitdiff \| raw \| diff to current
2021-02-27	Cesar Strauss	Add traces for the new FSM	blob \| commitdiff \| raw \| diff to current
2021-02-24	Tobias Platen	test_runner.py: add needed imports	blob \| commitdiff \| raw \| diff to current
2021-02-21	Cesar Strauss	Hide the register augmentation traces by default	blob \| commitdiff \| raw \| diff to current
2021-02-20	Luke Kenneth Casso...	whoops set ROM to none by mistake	blob \| commitdiff \| raw \| diff to current
2021-02-20	Luke Kenneth Casso...	remove massive code-duplication, move simple "self...	blob \| commitdiff \| raw \| diff to current
2021-02-17	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2021-02-17	Tobias Platen	add wishbone signals to gtkwave output	blob \| commitdiff \| raw \| diff to current
2021-02-17	Cesar Strauss	Add the SVSTATE traces to GTKWave to allow debugging...	blob \| commitdiff \| raw \| diff to current
2021-02-17	Cesar Strauss	Initialize the core SVSTATE from the corresponding...	blob \| commitdiff \| raw \| diff to current
2021-02-17	Cesar Strauss	Revert "Setup SVSTATE, from the test settings, at the...	blob \| commitdiff \| raw \| diff to current
2021-02-17	Cesar Strauss	Add traces to debug SVP64 prefix decoding issues	blob \| commitdiff \| raw \| diff to current
2021-02-17	Cesar Strauss	Setup SVSTATE, from the test settings, at the start	blob \| commitdiff \| raw \| diff to current
2021-02-16	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2021-02-15	Tobias Platen	test case for MMU SPRs: PID and PRTBL	blob \| commitdiff \| raw \| diff to current
2021-02-15	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2021-02-14	Cesar Strauss	Show traces for the register numbers of the current...	blob \| commitdiff \| raw \| diff to current
2021-02-14	Luke Kenneth Casso...	add TestRunner comments	blob \| commitdiff \| raw \| diff to current
2021-02-13	Luke Kenneth Casso...	split out TestRunner into separate module	blob \| commitdiff \| raw \| diff to current

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