add dummy call to simrun and end_test()
[soc.git] / src /
2021-10-08 Luke Kenneth Casso... add dummy call to simrun and end_test()
2021-10-08 Luke Kenneth Casso... code-comments and dummy functions
2021-10-08 Luke Kenneth Casso... move contents of run_sim_state into SimRunner run_test...
2021-10-08 Luke Kenneth Casso... add a SimRunner prepare_for_test and run_test function
2021-09-26 Las SafinAdd script for loading Libre-SOC onto Versa ECP5 board!
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-25 Las SafinUpdate libresoc-litex submodule
2021-09-25 Las SafinUpdate libresoc-litex submodule
2021-09-25 klehmanstart of HDLRunner
2021-09-24 Luke Kenneth Casso... create initial SimRunner
2021-09-24 Luke Kenneth Casso... add shiftrot2 tests to test_issuer.py
2021-09-23 Luke Kenneth Casso... move pc_i and svstate_i inside if self.run_hdl
2021-09-23 Luke Kenneth Casso... more comments
2021-09-23 Luke Kenneth Casso... add in a stack of comments for identifying match-points...
2021-09-23 Luke Kenneth Casso... add option to run ISACaller Sim (or not)
2021-09-23 Luke Kenneth Casso... add a new run_hdl parameter to TestRunner
2021-09-22 Luke Kenneth Casso... completely borked python segfault, workaround to copy...
2021-09-22 Luke Kenneth Casso... add test of expected results against last sim state
2021-09-22 Luke Kenneth Casso... whoops broken run_sim_state function
2021-09-22 Luke Kenneth Casso... split out HDL from Simulator into separate functions
2021-09-22 Luke Kenneth Casso... split out HDL test from Simulator test,
2021-09-22 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-22 Tobias Platencompldst_multi: add op_is_dcbz signal
2021-09-22 Jacob Lifshayfix mul fu test helper.py not passing immediate to...
2021-09-22 Tobias Platenwhitespace cleanup
2021-09-22 Luke Kenneth Casso... alter setup_tst_memory to take a test.mem rather than...
2021-09-22 Luke Kenneth Casso... whoops forgot to do with self.subTest()
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platentestcase: add mmu, link mmu and dcache together
2021-09-21 klehmanchanged test_runner to use state mem compare
2021-09-21 klehmanchanged over to use state mem compare
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platencomment out lines that cause test_compldst_multi_mmu...
2021-09-21 Luke Kenneth Casso... convert HDLState.get_mem() to a dictionary of memory...
2021-09-20 Tobias Platenupdate test_compldst_multi_mmu.py
2021-09-20 Luke Kenneth Casso... use get_l0_mem in HDLState to get memory data
2021-09-19 Cesar StraussFix rel_o/go_i signal names
2021-09-19 Cesar StraussReplace "Display" with "print" on simulation process
2021-09-19 Las SafinAdd ppc64le cross compiler
2021-09-19 Cesar StraussFix import
2021-09-18 Luke Kenneth Casso... allow individual unit tests to be named in test_issuer.py
2021-09-18 Luke Kenneth Casso... always store full memory state (including zeros)
2021-09-18 klehmanadded get_mem
2021-09-17 Luke Kenneth Casso... update comments
2021-09-16 Luke Kenneth Casso... moving teststate_check_regs written by klehman into...
2021-09-16 Las SafinSplit up into several derivations
2021-09-15 isengaaraMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-15 isengaaraadd new testcase for ompldst_multi using mmu
2021-09-14 Luke Kenneth Casso... convert to using TestState and State after moving to...
2021-09-14 klehmanfactory add and intro doc string
2021-09-12 Luke Kenneth Casso... use log instead of print
2021-09-12 Luke Kenneth Casso... code comments
2021-09-12 Luke Kenneth Casso... create new function teststate_check_regs which is calle...
2021-09-12 klehmanchanges to utilize full teststate class
2021-09-12 klehmanadded compare function
2021-09-12 klehmanadded factory function for test class creation
2021-09-10 klehmanimplement base class in state class
2021-09-10 klehmanchanges made to utilize teststate class
2021-09-10 Luke Kenneth Casso... update explanatory comments on LD/ST exception handling
2021-09-09 klehmanmade sim into generators and some uniformity changes
2021-09-09 klehmanfinished remaining hdl items
2021-09-09 klehmanHDL int reg added
2021-09-09 klehmanmore sim class registers add
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in...
2021-09-08 klehmaninitial commit of sim state class
2021-09-08 Cesar StraussMonitor the exception input to PowerDecoder2
2021-09-08 Cesar StraussRemove default argument for dict.get()
2021-09-07 Luke Kenneth Casso... fun fixing of get_core_hdl_regs, "yield from"
2021-09-07 Luke Kenneth Casso... move functions to above where they are called
2021-09-07 klehmanbreakout of register collection and compare
2021-09-07 Cesar StraussFix typo.
2021-09-07 Luke Kenneth Casso... add TODO code-comments
2021-09-07 Luke Kenneth Casso... whitespace, add bug ref number to test API
2021-09-03 Luke Kenneth Casso... another batch of ready/valid i/o prefix-suffix swaps
2021-08-31 Luke Kenneth Casso... anooother valid_o to convert to o_valid
2021-08-31 Luke Kenneth Casso... update ready/valid in shift_rot test_pipe_caller
2021-08-31 Jacob Lifshayfix test_all_values_covered, missed import when moving...
2021-08-30 Luke Kenneth Casso... update ready/valid i/o_ prefix in div test helper.py
2021-08-30 Luke Kenneth Casso... fix ready/valid i/o prefix in ALU test
2021-08-30 Luke Kenneth Casso... fix CR tests valid/ready naming
2021-08-30 Luke Kenneth Casso... missed valid/ready_i/o to o/i_ conversion
2021-08-30 Luke Kenneth Casso... missed valid/ready_i/o to o/i_ conversion
2021-08-29 Luke Kenneth Casso... unnecessary signal rename ivalid_i to ii_valid (reverting)
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-08-17 Tobias Platenfix "link addr-go direct to rel"
2021-08-17 Cesar StraussEnable LD/ST exception test case
2021-08-17 Cesar StraussClear operand latch on a terminating condition
2021-08-17 Cesar StraussAdd exc_o.happened to the conditions for terminating...
2021-08-17 Cesar StraussFix activation of cancel signal
2021-08-16 Cesar StraussAdjust PortInterface traces according to MMU option
2021-08-16 Tobias Platenfix renamed symbols
2021-08-16 Tobias Platenadd WIP DCBZTestCase
2021-08-01 Luke Kenneth Casso... move unused directory out of src, to indicate "ignore...
2021-08-01 Jonathan Neuschäferimport setup_i_memory from soc.simple.test.test_runner
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid...
2021-08-01 Jonathan NeuschäferRename test_dcache, which can't be invoked by test...
2021-08-01 Luke Kenneth Casso... simulator/test_sim.py should not have been added
2021-07-31 Tobias Platenpartial fix for src/soc/experiment/compldst_multi.py
2021-07-30 Tobias Platenpartially fix unit test in compldst_multi.py
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