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make bitmanip operations conditional on pspec.draft_bitmanip
[soc.git] / src /
2021-12-07 Jacob Lifshaymake bitmanip operations conditional on pspec.draft_bit... tree | commitdiff
2021-12-07 Jacob Lifshayformat code tree | commitdiff
2021-12-07 Jacob Lifshaymove rotator mode assignments as requested by lkcl tree | commitdiff
2021-12-07 Jacob Lifshayformat code tree | commitdiff
2021-12-07 Luke Kenneth Casso... tidyup, comments tree | commitdiff
2021-12-07 Luke Kenneth Casso... debug print tree | commitdiff
2021-12-06 Luke Kenneth Casso... another major bug, CacheTagArray valid was only 1 bit... tree | commitdiff
2021-12-06 Luke Kenneth Casso... tidyup: move hit_set to DCachePendingHit in dcache.py tree | commitdiff
2021-12-06 Luke Kenneth Casso... dcache.py tidyup tree | commitdiff
2021-12-06 Luke Kenneth Casso... rename dtlb to dtlb_valid and tidyup tree | commitdiff
2021-12-06 Luke Kenneth Casso... convert TLBArray to TLBValidArray tree | commitdiff
2021-12-06 Luke Kenneth Casso... convert DTLBUpdate to use a pair of Memorys tree | commitdiff
2021-12-06 Luke Kenneth Casso... more signals local to DTLBUpdate tree | commitdiff
2021-12-06 Luke Kenneth Casso... more signals local to DTLBUpdate tree | commitdiff
2021-12-06 Luke Kenneth Casso... update DTLBUpdate to reflect internal API now tree | commitdiff
2021-12-06 Luke Kenneth Casso... ooo nasty bug. used tlb_hit.way instead of tlb_hit... tree | commitdiff
2021-12-06 Luke Kenneth Casso... move DTLB Tags/Valids/PTEs into DTLBUpdate module tree | commitdiff
2021-12-06 Luke Kenneth Casso... start moving TLBArray into DTLBUpdate tree | commitdiff
2021-12-06 Luke Kenneth Casso... PLRUs were selecting an output index, only one selected tree | commitdiff
2021-12-06 Luke Kenneth Casso... repeated copies of read/write addr/sel to Cache SRAMs tree | commitdiff
2021-12-06 Luke Kenneth Casso... move bank of PLRUs to their own submodule in both dcach... tree | commitdiff
2021-12-06 Luke Kenneth Casso... code-comments tree | commitdiff
2021-12-06 Luke Kenneth Casso... use binary-to-unary encoders in dcache.py tree | commitdiff
2021-12-06 Luke Kenneth Casso... global (one) do_read signal in cache_rams dcache.py tree | commitdiff
2021-12-06 Luke Kenneth Casso... use one-hot binary-to-unary in dcache.py tree | commitdiff
2021-12-06 Luke Kenneth Casso... use i_in.req to gate hit_way via Decoder in icache.py tree | commitdiff
2021-12-06 Luke Kenneth Casso... use Decoder (binary-to-unary) in icache.py to deal... tree | commitdiff
2021-12-05 Luke Kenneth Casso... use unary encoding (one-hot) for replace_way hit_way... tree | commitdiff
2021-12-05 Luke Kenneth Casso... code-comments tree | commitdiff
2021-12-05 Luke Kenneth Casso... whitespace and minor cleanup of D-Cache tree | commitdiff
2021-12-05 Luke Kenneth Casso... more use of TLBHit Record in D-Cache tree | commitdiff
2021-12-05 Luke Kenneth Casso... correct tlb_hit_way and index sizes, use TLBHit Record... tree | commitdiff
2021-12-05 Luke Kenneth Casso... use TLBRecord in D-Cache for which TLB is selected tree | commitdiff
2021-12-05 Luke Kenneth Casso... split out TLBRecord, correct number of valid bits tree | commitdiff
2021-12-05 Luke Kenneth Casso... use Record in DCache for TLB tree | commitdiff
2021-12-05 Luke Kenneth Casso... use Record in D-Cache Cache Tags tree | commitdiff
2021-12-05 Luke Kenneth Casso... whitespace tree | commitdiff
2021-12-05 Luke Kenneth Casso... use Record for I-Cache Cache Tag/Valid tree | commitdiff
2021-12-05 Luke Kenneth Casso... whitespace tree | commitdiff
2021-12-05 Luke Kenneth Casso... use Record for ICache TLB tree | commitdiff
2021-12-05 Luke Kenneth Casso... sorting out test_mmu_dcache.py to use wb_get tree | commitdiff
2021-12-05 Luke Kenneth Casso... convert icache.py to standard wishbone Interface tree | commitdiff
2021-12-05 Luke Kenneth Casso... fake up wishbone stall signal in icache. tree | commitdiff
2021-12-05 Luke Kenneth Casso... fix icache row store issue tree | commitdiff
2021-12-05 Luke Kenneth Casso... using same tag/row functions as in dcache.py tree | commitdiff
2021-12-05 Luke Kenneth Casso... more signal sizes in icache.py tree | commitdiff
2021-12-05 Luke Kenneth Casso... incorrect Signal sizes in icache.py, tree | commitdiff
2021-12-05 Luke Kenneth Casso... sorting out icache.py, used to work tree | commitdiff
2021-12-05 Luke Kenneth Casso... remove redundant code tree | commitdiff
2021-12-05 Luke Kenneth Casso... add I-Cache standard bus (not used yet) tree | commitdiff
2021-12-05 Luke Kenneth Casso... remove yet another duplicate copy of wb_get, possible... tree | commitdiff
2021-12-05 Luke Kenneth Casso... replace yet another duplicate copy of wb_get, possible... tree | commitdiff
2021-12-05 Luke Kenneth Casso... wishbone bus convert on dcache tree | commitdiff
2021-12-05 Luke Kenneth Casso... correct import of wg_get function tree | commitdiff
2021-12-04 Luke Kenneth Casso... remove yet another duplicated copy of wb_get and add... tree | commitdiff
2021-12-04 Luke Kenneth Casso... rename function which needs replacing tree | commitdiff
2021-12-04 Luke Kenneth Casso... should have been using common version of wb_get, not... tree | commitdiff
2021-12-04 Luke Kenneth Casso... should not have been duplicating wb_get function in... tree | commitdiff
2021-12-04 Luke Kenneth Casso... get test_mmu_dcache.py working again tree | commitdiff
2021-12-04 Luke Kenneth Casso... remove wb_get, should not have been duplicated tree | commitdiff
2021-12-04 Luke Kenneth Casso... remove wb_get, should not have been massively duplicate... tree | commitdiff
2021-12-04 Luke Kenneth Casso... fix return results from pi_ld tree | commitdiff
2021-12-04 Luke Kenneth Casso... wark-wark, broke mmu with removing rin. reverted tree | commitdiff
2021-12-04 Tobias Platenfixed wait_addr to exit immediately on exception tree | commitdiff
2021-12-04 Luke Kenneth Casso... tidyup, comments tree | commitdiff
2021-12-04 Luke Kenneth Casso... tidyup mmu tree | commitdiff
2021-12-04 Luke Kenneth Casso... sigh in MMU FSM use direct access to ldst.dar/dsisr... tree | commitdiff
2021-12-04 Luke Kenneth Casso... remove DAR from PortInterface (where is the data going... tree | commitdiff
2021-12-04 Luke Kenneth Casso... stop using dar_o from PortInterface, get DAR directly... tree | commitdiff
2021-12-04 Luke Kenneth Casso... put DSISR and DAR publicly accessible in LoadStore1 tree | commitdiff
2021-12-04 Luke Kenneth Casso... whoops fix up exception happened if alignment triggers... tree | commitdiff
2021-12-04 Luke Kenneth Casso... fix pi_st which should not be trying to wait for the... tree | commitdiff
2021-12-04 Luke Kenneth Casso... fixing DAR updating from exceptions tree | commitdiff
2021-12-04 Luke Kenneth Casso... whoops tree | commitdiff
2021-12-04 Luke Kenneth Casso... MMU lookup DSISR load bit inverted in LoadStore1 tree | commitdiff
2021-12-04 Luke Kenneth Casso... store DAR in LoadStore1 tree | commitdiff
2021-12-04 Luke Kenneth Casso... not busy if excrption occurs on MMU_LOOKUP in loadstore.py tree | commitdiff
2021-12-04 Luke Kenneth Casso... add means to update dsisr from MMU FSM. TODO: add a... tree | commitdiff
2021-12-03 Luke Kenneth Casso... priv_mode/virt_mode are set in the request, which is... tree | commitdiff
2021-12-03 Luke Kenneth Casso... in loadstore.py set align_intr from request which comes... tree | commitdiff
2021-12-03 Luke Kenneth Casso... driver conflict on priv_mode and virt_mode, do not... tree | commitdiff
2021-12-03 Luke Kenneth Casso... fix up test_loadstore1.py tree | commitdiff
2021-12-03 Luke Kenneth Casso... in loadstore.py, when an exception is done or if the FSM tree | commitdiff
2021-12-03 Luke Kenneth Casso... fix PortInterfaceBase tree | commitdiff
2021-12-03 Luke Kenneth Casso... fix up LDST test functions pi_ld and pi_st to respect... tree | commitdiff
2021-12-03 Luke Kenneth Casso... whitespace tree | commitdiff
2021-12-03 Luke Kenneth Casso... add misaligned ld/st to trigger an exception tree | commitdiff
2021-12-03 Luke Kenneth Casso... comment out dsisr and dar in mmu FSM for now tree | commitdiff
2021-12-02 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-12-02 Tobias Platencleanup test_compldst_multi_mmu.py tree | commitdiff
2021-12-02 Luke Kenneth Casso... add a bitvector remap function, the plan is to use... tree | commitdiff
2021-12-02 Tobias Platenfix test_random in test_loadstore1 tree | commitdiff
2021-12-02 Luke Kenneth Casso... use new namedtuple in core when calling regspec_decode() tree | commitdiff
2021-12-02 Luke Kenneth Casso... add module parameter to regspec_decode and therefore... tree | commitdiff
2021-12-02 Jacob Lifshayremove bitmanip fu cuz ternlogi (the only instruction... tree | commitdiff
2021-12-02 Jacob Lifshayadd ternlogi to shiftrot tree | commitdiff
2021-12-02 Jacob Lifshayformat code tree | commitdiff
2021-12-01 Luke Kenneth Casso... stack of changes to MultiCompUnit to speed it up tree | commitdiff
2021-12-01 Luke Kenneth Casso... experimenting with option to shorten MultiCompUnit... tree | commitdiff
2021-12-01 Luke Kenneth Casso... create single-stage ALU pipeline, shorten latency on... tree | commitdiff
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