soc.git
5 years agoreset shadow latches if neither success nor fail are applied
Luke Kenneth Casson Leighton [Fri, 24 May 2019 11:40:28 +0000 (12:40 +0100)]
reset shadow latches if neither success nor fail are applied

5 years agosplit out shared wait for issue and wait for busy clear functions
Luke Kenneth Casson Leighton [Fri, 24 May 2019 09:06:39 +0000 (10:06 +0100)]
split out shared wait for issue and wait for busy clear functions

5 years agomake a start on a branch simulator
Luke Kenneth Casson Leighton [Fri, 24 May 2019 08:49:48 +0000 (09:49 +0100)]
make a start on a branch simulator

5 years agoadd simple branch-compare example ALU
Luke Kenneth Casson Leighton [Fri, 24 May 2019 07:56:59 +0000 (08:56 +0100)]
add simple branch-compare example ALU

5 years agoadd priority picker docstring
Luke Kenneth Casson Leighton [Fri, 24 May 2019 07:12:03 +0000 (08:12 +0100)]
add priority picker docstring

5 years agocleanup, docstrings
Luke Kenneth Casson Leighton [Fri, 24 May 2019 06:55:06 +0000 (07:55 +0100)]
cleanup, docstrings

5 years agoshadow seems to do the job of guaranteeing write-after-write
Luke Kenneth Casson Leighton [Thu, 23 May 2019 20:57:56 +0000 (21:57 +0100)]
shadow seems to do the job of guaranteeing write-after-write

5 years agoset up the shadow grid
Luke Kenneth Casson Leighton [Thu, 23 May 2019 14:19:49 +0000 (15:19 +0100)]
set up the shadow grid

5 years agoonly want a single-bit transition
Luke Kenneth Casson Leighton [Thu, 23 May 2019 13:27:10 +0000 (14:27 +0100)]
only want a single-bit transition

5 years agoadd in busy_prev/next signal to work out which unit was activated
Luke Kenneth Casson Leighton [Thu, 23 May 2019 13:23:32 +0000 (14:23 +0100)]
add in busy_prev/next signal to work out which unit was activated

5 years agoshadow fail/good signals need to be amalgamated (shadow enable is the matrix)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 12:55:38 +0000 (13:55 +0100)]
shadow fail/good signals need to be amalgamated (shadow enable is the matrix)

5 years agomake shadow inputs/good/fail arrays (actual matrix now)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 11:07:03 +0000 (12:07 +0100)]
make shadow inputs/good/fail arrays (actual matrix now)

5 years agodecide to do write-after-write shadows
Luke Kenneth Casson Leighton [Thu, 23 May 2019 10:58:19 +0000 (11:58 +0100)]
decide to do write-after-write shadows

5 years agoconnect FUFU/FURegs Matrices to resettable go_rd/go_wr (include go_die)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 09:28:40 +0000 (10:28 +0100)]
connect FUFU/FURegs Matrices to resettable go_rd/go_wr (include go_die)

5 years agostart wiring up shadow matrix
Luke Kenneth Casson Leighton [Thu, 23 May 2019 09:12:10 +0000 (10:12 +0100)]
start wiring up shadow matrix

5 years agore-enable shadow/go_die
Luke Kenneth Casson Leighton [Thu, 23 May 2019 08:58:14 +0000 (09:58 +0100)]
re-enable shadow/go_die

5 years agowhoops disconnected go_wr from CUs by mistake
Luke Kenneth Casson Leighton [Thu, 23 May 2019 08:52:14 +0000 (09:52 +0100)]
whoops disconnected go_wr from CUs by mistake

5 years agoadd shadow matrix (unconnected)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 08:44:42 +0000 (09:44 +0100)]
add shadow matrix (unconnected)

5 years agoadd shadow matrix, array of shadow functions
Luke Kenneth Casson Leighton [Thu, 23 May 2019 07:51:15 +0000 (08:51 +0100)]
add shadow matrix, array of shadow functions

5 years agoadd in shadown and go_die into comp unit
Luke Kenneth Casson Leighton [Thu, 23 May 2019 07:50:49 +0000 (08:50 +0100)]
add in shadown and go_die into comp unit

5 years agosplit out shadow into separate module
Luke Kenneth Casson Leighton [Thu, 23 May 2019 06:51:13 +0000 (07:51 +0100)]
split out shadow into separate module

5 years agosort out counter, rename data_o to data_r (register), document CompUnit
Luke Kenneth Casson Leighton [Wed, 22 May 2019 23:20:46 +0000 (00:20 +0100)]
sort out counter, rename data_o to data_r (register), document CompUnit

5 years agoinvert write pending before use
Luke Kenneth Casson Leighton [Wed, 22 May 2019 19:43:35 +0000 (20:43 +0100)]
invert write pending before use

5 years agotesting if hazard can be done in current cycle
Luke Kenneth Casson Leighton [Wed, 22 May 2019 19:18:08 +0000 (20:18 +0100)]
testing if hazard can be done in current cycle

5 years agouse global pending vectors for read/write pending accumulation
Luke Kenneth Casson Leighton [Wed, 22 May 2019 13:22:18 +0000 (14:22 +0100)]
use global pending vectors for read/write pending accumulation

5 years agoclean up names, also note that readable is true if no writes are pending
Luke Kenneth Casson Leighton [Wed, 22 May 2019 13:05:44 +0000 (14:05 +0100)]
clean up names, also note that readable is true if no writes are pending
and writable is true if no reads are pending

5 years agouse shifter opcode
Luke Kenneth Casson Leighton [Wed, 22 May 2019 12:36:39 +0000 (13:36 +0100)]
use shifter opcode

5 years agoignore self-to-self read and write pending hazards
Luke Kenneth Casson Leighton [Wed, 22 May 2019 12:24:01 +0000 (13:24 +0100)]
ignore self-to-self read and write pending hazards

5 years agoread-after-write self-referring hazard
Luke Kenneth Casson Leighton [Wed, 22 May 2019 12:09:49 +0000 (13:09 +0100)]
read-after-write self-referring hazard

5 years agoallow loops to run instruction batches more than once
Luke Kenneth Casson Leighton [Wed, 22 May 2019 10:56:56 +0000 (11:56 +0100)]
allow loops to run instruction batches more than once

5 years agoWaW needs to stall
Luke Kenneth Casson Leighton [Wed, 22 May 2019 10:10:13 +0000 (11:10 +0100)]
WaW needs to stall

5 years agowait for busy to go LOW before ending
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:43:43 +0000 (10:43 +0100)]
wait for busy to go LOW before ending

5 years agoexperiment with different completion times
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:43:20 +0000 (10:43 +0100)]
experiment with different completion times

5 years agoadd in 2 more ALUs, now 4x4 scoreboard
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:24:49 +0000 (10:24 +0100)]
add in 2 more ALUs, now 4x4 scoreboard

5 years agoadd mul and shift to simulation
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:00:50 +0000 (10:00 +0100)]
add mul and shift to simulation

5 years agoadd extra regression test
Luke Kenneth Casson Leighton [Wed, 22 May 2019 08:57:46 +0000 (09:57 +0100)]
add extra regression test

5 years agoadd div and shift (as experiment)
Luke Kenneth Casson Leighton [Wed, 22 May 2019 08:57:36 +0000 (09:57 +0100)]
add div and shift (as experiment)

5 years agohave to stop forward progress if issue is set
Luke Kenneth Casson Leighton [Wed, 22 May 2019 07:34:12 +0000 (08:34 +0100)]
have to stop forward progress if issue is set

5 years agorandom regression test shows an inter-dependency fail
Luke Kenneth Casson Leighton [Wed, 22 May 2019 06:27:37 +0000 (07:27 +0100)]
random regression test shows an inter-dependency fail

5 years agoworking on all cycles, RaW / WaR
Luke Kenneth Casson Leighton [Tue, 21 May 2019 22:59:53 +0000 (23:59 +0100)]
working on all cycles, RaW / WaR

5 years agogot working (sort-of) cscore6600
Luke Kenneth Casson Leighton [Tue, 21 May 2019 22:54:02 +0000 (23:54 +0100)]
got working (sort-of) cscore6600

5 years agogot working (sort-of) cscore6600
Luke Kenneth Casson Leighton [Tue, 21 May 2019 22:53:53 +0000 (23:53 +0100)]
got working (sort-of) cscore6600

5 years agoadd read/write reg select vectors, in and out, similar to FunctionUnit
Luke Kenneth Casson Leighton [Tue, 21 May 2019 09:32:23 +0000 (10:32 +0100)]
add read/write reg select vectors, in and out, similar to FunctionUnit

5 years agouse dep cell format
Luke Kenneth Casson Leighton [Mon, 20 May 2019 20:00:52 +0000 (21:00 +0100)]
use dep cell format

5 years agoinvert x/y in fu pending
Luke Kenneth Casson Leighton [Mon, 20 May 2019 11:11:30 +0000 (12:11 +0100)]
invert x/y in fu pending

5 years agonearly there with readable/writable on FU matrix
Luke Kenneth Casson Leighton [Mon, 20 May 2019 10:19:13 +0000 (11:19 +0100)]
nearly there with readable/writable on FU matrix

5 years agoattempting to work out FU-FU matrix connections
Luke Kenneth Casson Leighton [Mon, 20 May 2019 08:07:44 +0000 (09:07 +0100)]
attempting to work out FU-FU matrix connections

5 years agoinclude hazard line to swap rd/wr dependencies
Luke Kenneth Casson Leighton [Mon, 20 May 2019 07:49:48 +0000 (08:49 +0100)]
include hazard line to swap rd/wr dependencies

5 years agonon-overlapping instructions ok
Luke Kenneth Casson Leighton [Sun, 19 May 2019 16:43:05 +0000 (17:43 +0100)]
non-overlapping instructions ok

5 years agosync ok on simple add
Luke Kenneth Casson Leighton [Sun, 19 May 2019 15:34:50 +0000 (16:34 +0100)]
sync ok on simple add

5 years agoadd reg clearing and read-request release
Luke Kenneth Casson Leighton [Sun, 19 May 2019 15:11:51 +0000 (16:11 +0100)]
add reg clearing and read-request release

5 years agouse register-based DepCell
Luke Kenneth Casson Leighton [Sun, 19 May 2019 09:34:02 +0000 (10:34 +0100)]
use register-based DepCell

5 years agocreating separate dependency cell which can be used for all 3 src1/src2/dest
Luke Kenneth Casson Leighton [Sun, 19 May 2019 08:19:40 +0000 (09:19 +0100)]
creating separate dependency cell which can be used for all 3 src1/src2/dest

5 years agoexperiment switching over fwd and rsel in dependency cell
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:15:39 +0000 (07:15 +0100)]
experiment switching over fwd and rsel in dependency cell

5 years agoadd individual dependency cell (sync mode)
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:15:12 +0000 (07:15 +0100)]
add individual dependency cell (sync mode)

5 years agoscoreboard 6600 experimentation
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:14:31 +0000 (07:14 +0100)]
scoreboard 6600 experimentation

5 years agowhoops bug where rsel lists were being re-initialised to empty
Luke Kenneth Casson Leighton [Sat, 18 May 2019 14:53:57 +0000 (15:53 +0100)]
whoops bug where rsel lists were being re-initialised to empty

5 years agoreduce length of vectors (per-row only single bit)
Luke Kenneth Casson Leighton [Sat, 18 May 2019 11:38:56 +0000 (12:38 +0100)]
reduce length of vectors (per-row only single bit)

5 years agoconnect up vectors direct
Luke Kenneth Casson Leighton [Sat, 18 May 2019 09:12:23 +0000 (10:12 +0100)]
connect up vectors direct

5 years agoconnect dependency row outputs
Luke Kenneth Casson Leighton [Sat, 18 May 2019 09:03:46 +0000 (10:03 +0100)]
connect dependency row outputs

5 years agocompress dependency matrix outputs into a row
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:53:10 +0000 (09:53 +0100)]
compress dependency matrix outputs into a row

5 years agomove dependency cells to row class
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:43:27 +0000 (09:43 +0100)]
move dependency cells to row class

5 years agoRevert "whoops use global vector correctly"
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:19:54 +0000 (09:19 +0100)]
Revert "whoops use global vector correctly"

This reverts commit d6723d9007b9fb5b9f56290e26af3e6bfa4f69f1.

5 years agowhoops use global vector correctly
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:18:03 +0000 (09:18 +0100)]
whoops use global vector correctly

5 years agowhoops use global vector correctly
Luke Kenneth Casson Leighton [Sat, 18 May 2019 07:47:29 +0000 (08:47 +0100)]
whoops use global vector correctly

5 years agoreduce syncs, get FU-FU and FU on same clock cycle
Luke Kenneth Casson Leighton [Sat, 18 May 2019 07:00:03 +0000 (08:00 +0100)]
reduce syncs, get FU-FU and FU on same clock cycle

5 years agonow using readable/writable from fu-fu matrix, seems to be working
Luke Kenneth Casson Leighton [Sat, 18 May 2019 06:50:36 +0000 (07:50 +0100)]
now using readable/writable from fu-fu matrix, seems to be working

5 years agouse FU-FU matrix, seems to be working, still have to resolve dependencies
Luke Kenneth Casson Leighton [Sat, 18 May 2019 05:29:08 +0000 (06:29 +0100)]
use FU-FU matrix, seems to be working, still have to resolve dependencies

5 years agouse FU-FU matrix, seems to be working, still have to resolve dependencies
Luke Kenneth Casson Leighton [Sat, 18 May 2019 05:29:01 +0000 (06:29 +0100)]
use FU-FU matrix, seems to be working, still have to resolve dependencies

5 years agoreorg instr test issue
Luke Kenneth Casson Leighton [Thu, 16 May 2019 15:41:53 +0000 (16:41 +0100)]
reorg instr test issue

5 years agoadd back in rd-flag qualification into fn unit
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:34:31 +0000 (12:34 +0100)]
add back in rd-flag qualification into fn unit

5 years agobring in go_rd_i into 6600 scoreboard, on 1-clock delay
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:07:43 +0000 (12:07 +0100)]
bring in go_rd_i into 6600 scoreboard, on 1-clock delay

5 years agoand in go_rd_i into group picker read
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:07:02 +0000 (12:07 +0100)]
and in go_rd_i into group picker read

5 years agoremove & rd_l.q, is now in group picker
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:06:45 +0000 (12:06 +0100)]
remove & rd_l.q, is now in group picker

5 years agoadd in go_rd
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:02:36 +0000 (12:02 +0100)]
add in go_rd

5 years agoexperiment lock out of registers in read vector
Luke Kenneth Casson Leighton [Thu, 16 May 2019 06:58:48 +0000 (07:58 +0100)]
experiment lock out of registers in read vector

5 years agosync function unit src/dest
Luke Kenneth Casson Leighton [Thu, 16 May 2019 04:22:07 +0000 (05:22 +0100)]
sync function unit src/dest

5 years agogetting there with instruction overlapping
Luke Kenneth Casson Leighton [Thu, 16 May 2019 04:02:23 +0000 (05:02 +0100)]
getting there with instruction overlapping

5 years agotry random inputs
Luke Kenneth Casson Leighton [Wed, 15 May 2019 17:13:01 +0000 (18:13 +0100)]
try random inputs

5 years agowrite-after-read hazard working
Luke Kenneth Casson Leighton [Wed, 15 May 2019 15:23:43 +0000 (16:23 +0100)]
write-after-read hazard working

5 years agomake global pending sync-delayed
Luke Kenneth Casson Leighton [Wed, 15 May 2019 15:11:46 +0000 (16:11 +0100)]
make global pending sync-delayed

5 years agomake fn unit invert readable, however qualify with rd latch
Luke Kenneth Casson Leighton [Wed, 15 May 2019 15:06:47 +0000 (16:06 +0100)]
make fn unit invert readable, however qualify with rd latch

5 years agoincrease counter, experiment with longer completion times
Luke Kenneth Casson Leighton [Wed, 15 May 2019 07:29:00 +0000 (08:29 +0100)]
increase counter, experiment with longer completion times

5 years agovery weird: invert readable vector, cscore works
Luke Kenneth Casson Leighton [Wed, 15 May 2019 06:48:51 +0000 (07:48 +0100)]
very weird: invert readable vector, cscore works

5 years agoexperimenting with cscore, overlapping instructions
Luke Kenneth Casson Leighton [Tue, 14 May 2019 09:35:41 +0000 (10:35 +0100)]
experimenting with cscore, overlapping instructions

5 years agoinverted global write pend vector, on creation of readable signal,
Luke Kenneth Casson Leighton [Tue, 14 May 2019 09:02:54 +0000 (10:02 +0100)]
inverted global write pend vector, on creation of readable signal,
seems to work

5 years agoexperimenting with score6600
Luke Kenneth Casson Leighton [Tue, 14 May 2019 09:02:18 +0000 (10:02 +0100)]
experimenting with score6600

5 years agoexperimenting with cscore
Luke Kenneth Casson Leighton [Tue, 14 May 2019 04:37:09 +0000 (05:37 +0100)]
experimenting with cscore

5 years agolatch Function Unit registers based on "issue" signal
Luke Kenneth Casson Leighton [Tue, 14 May 2019 04:27:09 +0000 (05:27 +0100)]
latch Function Unit registers based on "issue" signal

5 years agocomb on intpick
Luke Kenneth Casson Leighton [Mon, 13 May 2019 22:24:07 +0000 (23:24 +0100)]
comb on intpick

5 years agoscore6600 working without FunctionUnit (using dep matrices)
Luke Kenneth Casson Leighton [Mon, 13 May 2019 22:08:16 +0000 (23:08 +0100)]
score6600 working without FunctionUnit (using dep matrices)

5 years agosync on req_rel
Luke Kenneth Casson Leighton [Mon, 13 May 2019 21:07:54 +0000 (22:07 +0100)]
sync on req_rel

5 years agoreturn to latch on src for oper
Luke Kenneth Casson Leighton [Mon, 13 May 2019 21:07:38 +0000 (22:07 +0100)]
return to latch on src for oper

5 years agorename intermediate signals to wr_wait/rd_wait
Luke Kenneth Casson Leighton [Mon, 13 May 2019 19:03:23 +0000 (20:03 +0100)]
rename intermediate signals to wr_wait/rd_wait

5 years agosplit out readable/writable setup
Luke Kenneth Casson Leighton [Mon, 13 May 2019 19:01:29 +0000 (20:01 +0100)]
split out readable/writable setup

5 years agogo_rd/go_wr not arrays any more
Luke Kenneth Casson Leighton [Mon, 13 May 2019 14:32:18 +0000 (15:32 +0100)]
go_rd/go_wr not arrays any more

5 years agouse operand latch, seems to work (6600 not cscore)
Luke Kenneth Casson Leighton [Mon, 13 May 2019 13:38:15 +0000 (14:38 +0100)]
use operand latch, seems to work (6600 not cscore)

5 years agoadd fn-unit src/dest latch registers
Luke Kenneth Casson Leighton [Mon, 13 May 2019 13:20:41 +0000 (14:20 +0100)]
add fn-unit src/dest latch registers

5 years agomake read/write-pending syncd
Luke Kenneth Casson Leighton [Mon, 13 May 2019 07:38:58 +0000 (08:38 +0100)]
make read/write-pending syncd

5 years agouse signals instead of arrays
Luke Kenneth Casson Leighton [Mon, 13 May 2019 07:30:01 +0000 (08:30 +0100)]
use signals instead of arrays