| 2021-05-12 |
Luke Kenneth Casson... | add dcache tlb / pte test
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | set m_out.load from ldst_r(egister) in LoadStore1
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | move dcache unit test to separate test_dcache.py
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | experimentation with MMU-enabled LoadStore1 through...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | add debug info, update comments, disable dcache in...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | start doing virtual memory queries via PortInterface...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | whoops missing default zero (no idea how)
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | addcomments for MMU PortInterface test (how it, um...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | bit of a hack to get test_mmu_dcache_pi.py operational.
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | no need for sel0
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | pass through MSR.PR through PortInterface, into LoadStore1
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | connect MSR.PR to PortInterface in LDSTCompUnit
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | add msr_pr bit in PortInterface
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | add MSR to LD/ST Input Record
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | comment tidyup
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | must also pass through instruction fault exception...
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | whoops names changed in MMU FSM
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | tidyup comments and remove LoadStore COMPLETE state
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | cleanup on exception setting
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | rename LoadStore1 data structures back to microwatt...
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | add block for MMU activation to LoadStore1
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | move LoadStore1 d_validblip setting, and get MMU_LOOKUP...
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | whoops, indentation issue on m.If/m.Else in dcache.py
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | add links to set associative image, and bugreport
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comments on translation of MMU_LOOKUP
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | install MMU_LOOKUP vhdl to be translated to nmigen
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | move (unused) ACK_WAIT code into FSM
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comments in LoadStore1
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | remove invalid setting of d_in.valid from self.mmureq
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | no SECOND_REQ
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | remove SECOND_REQ
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comment about LD/ST exception needs copying into...
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | run LD/ST Exception test case for MMU
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add MMU bugtracker link
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | git submodule update
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | update code-comments
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add in alignment exception capture/reporting in LoadStore1
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | preference is to create a temp variable for comb and...
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add misalign flag to PortInterfaceBase
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | LoadStore1 tidyup
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | transferring more over to LoadStore FSM
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | start putting state info into LoadStore1, slowly putting...
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | add LoadStore State enum
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | add bugreport link to mmu
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | start setting DSISR bits but commented out
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | update comments and docstrings
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops, import error
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move LoadStore1 class to soc.fu.ldst.loadstore
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops was still copying output over in CommonOutputStage
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | how we managed to get this far without noticing that...
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move dsisr and dar into LoadStore1
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move zero-dest-pred in Common Output Stage to not copy...
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops setup of core.sv_pred_sm/dm not indented and...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | whoops disabled tests agaaaaain
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass relevant predicate mask bits through to Decoders...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | add in predicate mask bit detection when zeroing is...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass SVP64 ReMap field through to core and then on...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | moved exts* SVP64 unit tests to a different location
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | argh someobe falsely stated in the README that LibreSOC...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | if zeroing is set, put zero into input or output as...
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | simplify README.md so that it gets submitted to pypi
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | mark long description type as markdown
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | update NEWS.txt
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | add libresoc-openpower-isa to setup.py dependencies
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | put sv_input_record_layout onto CompOpSubsetBase after all
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | whoops wrong signal name, set exc_happened
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | add SVP64 RM fields to ALU input record
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | remove minerva debug unit (not needed)
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | whoops disabled some test_issuer group tests
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add SVSTATE (SVSRR0) to TRAP pipeline
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | adding fast3 SPR to Trap pipeline and unit test
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | new fast3 needs to be remapped to fast1 port in "reduced...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | missed that soc.regfile.util has moved to openpower...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add SVSRR0 to FastRegsEnum
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add TODO comments and cross-reference to bug
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | note a way to see if an exception happened, in TestIssuer
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add printout showing exception output from FUs
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | remove symlink
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add links in README
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | more rename of exception_o to exc_o, add convenience...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | wire in exc_o.happened into write-cancellation of LDSTCompUnit
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | comments, and change name of LDSTCompUnit exception_o...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | remove exception from data on FUBaseData, explicitly...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | code-comments for LDSTCompUnit
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add LDSTException class to LDSTOutputData
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add option to add exception type to FUBaseData (pipe_data)
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | rename IntegerData to FUBaseData
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | comment out nc (nocache), it seems to actually work
|
commit | commitdiff | tree |
| 2021-05-03 |
Luke Kenneth Casson... | MMU: get store to activate only when data is available...
|
commit | commitdiff | tree |
| 2021-05-03 |
Luke Kenneth Casson... | disable the cache for now, whilst testing read/write...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | use Const to define bit-length when comparing top nibble...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | mmu FSM store in dcache: only put data onto d_in on...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | return d_out.valid instead of always "ok" in MMU FSM
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | HACK WARNING: disable d-cache on hard-coded address...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | add nc argument to dcache load/store tests
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | quick hack to SRAM test and to dcache to enable classic...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | adjust dependencies in setup.py
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | enable issuer_verilog.py to generate new MMU/DCache...
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | send a DMI RESET at the end of the test.
|
commit | commitdiff | tree |
| next |
projects / soc.git / search