| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Rewrite git://git.libre-riscv.org URLs...
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| 2021-05-04 |
Luke Kenneth Casson... | whoops disabled some test_issuer group tests
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| 2021-05-04 |
Luke Kenneth Casson... | add SVSTATE (SVSRR0) to TRAP pipeline
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| 2021-05-04 |
Luke Kenneth Casson... | adding fast3 SPR to Trap pipeline and unit test
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| 2021-05-04 |
Luke Kenneth Casson... | new fast3 needs to be remapped to fast1 port in "reduced...
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| 2021-05-04 |
Luke Kenneth Casson... | missed that soc.regfile.util has moved to openpower...
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| 2021-05-04 |
Luke Kenneth Casson... | add SVSRR0 to FastRegsEnum
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| 2021-05-04 |
Luke Kenneth Casson... | add TODO comments and cross-reference to bug
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| 2021-05-04 |
Luke Kenneth Casson... | note a way to see if an exception happened, in TestIssuer
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| 2021-05-04 |
Luke Kenneth Casson... | add printout showing exception output from FUs
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| 2021-05-04 |
Luke Kenneth Casson... | remove symlink
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| 2021-05-04 |
Luke Kenneth Casson... | add links in README
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| 2021-05-04 |
Luke Kenneth Casson... | more rename of exception_o to exc_o, add convenience...
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| 2021-05-04 |
Luke Kenneth Casson... | wire in exc_o.happened into write-cancellation of LDSTCompUnit
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| 2021-05-04 |
Luke Kenneth Casson... | comments, and change name of LDSTCompUnit exception_o...
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| 2021-05-04 |
Luke Kenneth Casson... | remove exception from data on FUBaseData, explicitly...
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| 2021-05-04 |
Luke Kenneth Casson... | code-comments for LDSTCompUnit
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| 2021-05-04 |
Luke Kenneth Casson... | add LDSTException class to LDSTOutputData
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| 2021-05-04 |
Luke Kenneth Casson... | add option to add exception type to FUBaseData (pipe_data)
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| 2021-05-04 |
Luke Kenneth Casson... | rename IntegerData to FUBaseData
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| 2021-05-04 |
Luke Kenneth Casson... | comment out nc (nocache), it seems to actually work
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| 2021-05-03 |
Luke Kenneth Casson... | MMU: get store to activate only when data is available...
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| 2021-05-03 |
Luke Kenneth Casson... | disable the cache for now, whilst testing read/write...
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| 2021-05-02 |
Luke Kenneth Casson... | use Const to define bit-length when comparing top nibble...
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| 2021-05-02 |
Luke Kenneth Casson... | mmu FSM store in dcache: only put data onto d_in on...
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| 2021-05-02 |
Luke Kenneth Casson... | return d_out.valid instead of always "ok" in MMU FSM
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| 2021-05-02 |
Luke Kenneth Casson... | HACK WARNING: disable d-cache on hard-coded address...
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| 2021-05-02 |
Luke Kenneth Casson... | add nc argument to dcache load/store tests
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| 2021-05-02 |
Luke Kenneth Casson... | quick hack to SRAM test and to dcache to enable classic...
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| 2021-05-02 |
Luke Kenneth Casson... | adjust dependencies in setup.py
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| 2021-05-01 |
Luke Kenneth Casson... | enable issuer_verilog.py to generate new MMU/DCache...
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| 2021-05-01 |
Luke Kenneth Casson... | send a DMI RESET at the end of the test.
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| 2021-05-01 |
Luke Kenneth Casson... | store data in microwatt dcache goes in one cycle AFTER...
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| 2021-05-01 |
Luke Kenneth Casson... | dcache store test: data goes in one cycle AFTER valid...
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| 2021-05-01 |
Luke Kenneth Casson... | only do dcache lookup for now
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| 2021-05-01 |
Luke Kenneth Casson... | add LD/ST cases to MMU, which should all still work
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| 2021-05-01 |
Luke Kenneth Casson... | add MMUTestCaseROM
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| 2021-05-01 |
Luke Kenneth Casson... | whitespace
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| 2021-05-01 |
Luke Kenneth Casson... | use new AllFunctionUnits.get_fu function
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| 2021-05-01 |
Luke Kenneth Casson... | use SPRreduced to match PowerDecoder2
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| 2021-05-01 |
Luke Kenneth Casson... | missing self.
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| 2021-05-01 |
Luke Kenneth Casson... | resolve DriverConflict in TstL0CacheBuffer, really...
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| 2021-04-30 |
Luke Kenneth Casson... | debug and stop on mmu test_pipe_caller.py
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| 2021-04-30 |
Luke Kenneth Casson... | comments on dcache-to-mmu link
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| 2021-04-30 |
Luke Kenneth Casson... | add a TestSRAM variant of LoadStore1, for being able...
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| 2021-04-30 |
Luke Kenneth Casson... | add basic test_issuer_mmu.py
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| 2021-04-30 |
Luke Kenneth Casson... | add option to use new mmu_cache_wb ConfigMemoryPortInterface
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| 2021-04-30 |
Luke Kenneth Casson... | hook up dcache wb_in/out to PortInterfaceBase Wishbone...
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| 2021-04-30 |
Luke Kenneth Casson... | sort out spblock 4k sram cell instance name to match...
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| 2021-04-30 |
Luke Kenneth Casson... | https://bugs.libre-soc.org/show_bug.cgi?id=635
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| 2021-04-30 |
Luke Kenneth Casson... | better reporting on gpr comparisons
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| 2021-04-30 |
Luke Kenneth Casson... | set up LoadStore1 in ConfigMemoryPortInterface and...
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| 2021-04-29 |
Luke Kenneth Casson... | comment out adding mmu and dcache to pspec in MMU FSM
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| 2021-04-29 |
Luke Kenneth Casson... | move dcache into Loadstore1
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| 2021-04-27 |
Luke Kenneth Casson... | add option to disable bus forwarding on SPRs and FAST...
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| 2021-04-27 |
Luke Kenneth Casson... | add option to enable/disable bus forwarding mode on...
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| 2021-04-27 |
Luke Kenneth Casson... | return read data out from Loadstore1 only when valid
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| 2021-04-26 |
Luke Kenneth Casson... | hook up MSR into MMU (TODO, use a lot less bits)
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| 2021-04-26 |
Luke Kenneth Casson... | simple regression dcache test was faulty. wishbone...
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| 2021-04-26 |
Luke Kenneth Casson... | comment read ack in sram
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| 2021-04-26 |
Luke Kenneth Casson... | incorrect indentation in dcache rams
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| 2021-04-26 |
Luke Kenneth Casson... | simplify dcache test
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| 2021-04-25 |
Luke Kenneth Casson... | spelling mistake
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| 2021-04-25 |
Luke Kenneth Casson... | remove RegStage1.real_adr temporary from dcache
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| 2021-04-25 |
Luke Kenneth Casson... | do not overwrite parameter ra in dcache
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| 2021-04-25 |
Luke Kenneth Casson... | comment out dcache_store from test, not the problem
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| 2021-04-25 |
Luke Kenneth Casson... | remove unneeded code
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| 2021-04-25 |
Luke Kenneth Casson... | read req in wb_in.stall, dcache
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| 2021-04-25 |
Luke Kenneth Casson... | add single regression test for dcache
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| 2021-04-25 |
Luke Kenneth Casson... | add TODO comment in dcache
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| 2021-04-25 |
Luke Kenneth Casson... | move Signals in dcache to relevant context
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| 2021-04-25 |
Luke Kenneth Casson... | dcache Elif used where If should have been
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| 2021-04-25 |
Luke Kenneth Casson... | whoops should be cyc & ~ack
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| 2021-04-25 |
Luke Kenneth Casson... | hard-code dcache stall signal to non-pipelined mode
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| 2021-04-24 |
Luke Kenneth Casson... | increase memory size in dcache test
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| 2021-04-24 |
Luke Kenneth Casson... | increase size of random dcache testing by 10
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| 2021-04-24 |
Luke Kenneth Casson... | fix errors in dcache unit test
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| 2021-04-24 |
Luke Kenneth Casson... | whitespace
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| 2021-04-24 |
Luke Kenneth Casson... | add additional external libre-soc sphinx references...
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| 2021-04-24 |
Luke Kenneth Casson... | add additional external libre-soc sphinx references
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| 2021-04-24 |
Luke Kenneth Casson... | remove code moved to openpower-isa repo
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| 2021-04-23 |
Luke Kenneth Casson... | add comments on TestIssuer TestRunner
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| 2021-04-23 |
Luke Kenneth Casson... | comment tests back in
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| 2021-04-23 |
Luke Kenneth Casson... | fix import error
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| 2021-04-23 |
Luke Kenneth Casson... | error in setting fast regs test values
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| 2021-04-23 |
Luke Kenneth Casson... | import from openpower.tests
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| 2021-04-23 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-04-23 |
Luke Kenneth Casson... | move logical tests to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | add trap test cases
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commit | commitdiff | tree |
| 2021-04-23 |
Luke Kenneth Casson... | move SPR tests to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move branch test cases to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move LDST tests to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move mul tests to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move div tests to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move div tests to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move ALU test cases to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move MMU Testcase to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move CR test cases to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | move shiftrot test cases to openpower.test
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| 2021-04-23 |
Luke Kenneth Casson... | import from openpower.endian
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