riscv-isa-sim.git
2013-07-13 Andrew WatermanEliminate infinite loop in debug mode
2013-07-13 Andrew WatermanExit cleanly from debug console
2013-07-13 Andrew WatermanFavor procs.size() over num_cores()
2013-07-13 Andrew WatermanFix SR_U64 bit being ignored
2013-06-03 Andrew Watermanmake spike.o correctly depend on dispatch.h
2013-06-03 Andrew Watermanuse coreutils `seq' instead of hacky `range'
2013-05-15 Yunsup Leechange riscv-isa-run to spike in documentation
2013-05-15 Yunsup Leefix make issue
2013-05-14 Yunsup Leechange riscv-isa-run to spike
2013-05-06 Andrew Watermanmake Makefile sh-friendly
2013-04-25 Andrew Watermanuse inttypes macros to print uint64_t
2013-04-25 Andrew Watermanfix(?) circular dependence on generated headers
2013-04-25 Andrew Watermanadd range(start, end) method to Makefile
2013-04-24 Yunsup Leefixes to correctly simulate the vector unit
2013-04-23 Andrew Watermanmake interactive mode cope with canonical terminal
2013-04-23 Andrew Watermandestroy htif on simulator termination
2013-04-22 Andrew Watermancorrectly depend on dispatch.h
2013-04-20 Andrew Watermanremove circular dependence in Makefile
2013-04-20 Andrew Watermanupdate abi register names
2013-04-17 Andrew Watermanadd AUIPC insn; remove RDNPC insn
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-30 Andrew Watermanignore writes to SR IP field
2013-03-27 Andrew Watermanopcodes.h must only contain DECLARE_INSN() lines
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermanupdate ancient README
2013-03-26 Andrew Watermantruncate effective addresses in rv32
2013-03-26 Andrew Watermanexpose pending interrupts in status register
2013-03-26 Andrew Watermanadd missing #include
2013-03-26 Andrew Watermanignore host writes to fromhost if old value not 0
2013-03-26 Andrew Watermansupport compilation with gcc 4.7
2013-02-15 Andrew Watermanfix D$ model not acknowledging stores
2013-02-15 Andrew Watermanspecialize fully-associative caches
2013-02-15 Andrew Watermandon't store host pointers in soft TLB
2013-02-13 Andrew Watermanclean up fetch-execute loop a bit
2013-02-13 Andrew Watermanadd I$/D$/L2$ simulators
2013-02-13 Andrew Watermanmigrate to c++11
2013-02-13 Andrew Watermanmake HTIF interactions deterministic; fix race
2013-01-26 Andrew Watermanremove unnecessary #include
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-11-13 Yunsup Leefix vector code simulation problem, turn on SR_U64
2012-08-31 Andrew Watermannew tohost/fromhost semantics
2012-08-02 Andrew Watermannew tohost/fromhost semantics
2012-07-23 Andrew Watermancorrect HTIF reset behavior
2012-05-16 Andrew Watermanfix htif interaction with interactive mode
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2012-03-24 Yunsup Leeadd disasm functions for vector
2012-03-20 Andrew Watermanmake NaN behavior consistent with hardfloat
2012-03-20 Andrew Watermanfix double-precision NaNs
2012-03-20 Andrew Watermanabstract regfile write port
2012-03-20 Andrew Watermanabstract regfile behind object
2012-03-19 Andrew Watermanupdate vector fences
2012-03-18 Yunsup Leeclean up vector exception instructions
2012-03-14 Yunsup Leeadd more instructions for vector exception handling
2012-03-14 Yunsup Leeadd vvcfg,vtcfg
2012-03-13 Yunsup Leeopcodes cleanup
2012-03-13 Andrew Watermanalways propagate default NaN (all bits set)
2012-03-10 Yunsup Leeslight change to vector supervisor instructions
2012-03-03 Yunsup Leeadd place holders for instructions to handle vector...
2012-03-03 Yunsup Leenew instructions to handle vector exceptions
2012-02-20 Andrew Watermannew HTIF protocol. update your fesvr.
2012-02-20 Andrew Watermanfixed a bug in remu[w]
2012-02-18 Andrew Watermanimplement lighter-weight htif packet header
2012-02-16 Andrew Watermanreimplement div[u][w]/rem[u][w]
2012-02-13 Andrew Watermanfix sltu disassembly
2012-02-09 Yunsup Leeinitialize tohost and fromhost
2012-02-01 Andrew Watermanremove debug printf
2012-02-01 Andrew Watermanpoll HTIF occasionally
2012-01-31 Andrew Watermandon't set badvaddr for instruction access faults
2012-01-30 Yunsup Leefix divide by zero bugs
2012-01-24 Andrew Watermancheck that virtual addresses are sign-extended
2012-01-23 Andrew Watermandisentangle decode.h from other headers
2012-01-23 Andrew Watermanwork around gcc 4.4 bug
2012-01-12 Andrew Watermanfix compilation for gcc 4.6.1
2011-12-11 Yunsup Leefix utidx assign bug, make ut code execute faster
2011-12-11 Yunsup Leefix the fpr abi names
2011-11-12 Your NameRemove dependence on binutils
2011-11-11 Andrew WatermanUse new compiler toolchain's disassembler
2011-11-11 Andrew WatermanChanged MFTX to use rs1 for its source
2011-11-11 Andrew WatermanChanged supervisor mode
2011-11-01 Andrew WatermanFixed tight coupling of host and target page size
2011-10-27 Andrew Watermanchanged page size to 8KB
2011-10-19 Yunsup LeeMerge branch 'master' of github.com:ucb-bar/riscv-isa-sim
2011-10-19 Yunsup Leefix vf
2011-10-19 Yunsup Leeyunsup made this fix..ask him
2011-08-18 Andrew Watermandon't forget to commit configure after autoconf!
2011-07-13 Rimas Avizienisadded #include <stdlib.h> to get rid of errors building...
2011-07-08 Rimas Avizienisbugfix to riscv.ac
2011-07-08 Rimas Avizienisfixes to make disassembly work under macos (with macpor...
2011-06-27 Andrew WatermanBuilds and runs on Mac OS 10.6.7
2011-06-20 Andrew Watermanpost-repo-split cleanup
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-12 Andrew Waterman[xcc] fixed simulator build time
2011-06-12 Andrew Waterman[xcc] tlb now stores host addresses
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-06-11 Andrew Waterman[xcc] fix configure scripts
2011-06-11 Andrew Waterman[xcc] instructions now set PC explicitly
2011-06-11 Andrew Waterman[sim, opcodes] made sim more decoupled from opcodes
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