clarifyg

diff --git a/updates/023_2020mar26_decoder_emulator_started.mdwn b/updates/023_2020mar26_decoder_emulator_started.mdwn
index 8783a570f9fb8c3f7cdf6b4d88bb8669bc0f3c7e..7dc701bb08e68eab235d7ba71736928c6ad8a6ab 100644 (file)
--- a/updates/023_2020mar26_decoder_emulator_started.mdwn
+++ b/updates/023_2020mar26_decoder_emulator_started.mdwn
@@ -352,8 +352,10 @@ as well as the key differences is particularly important.  At the very least,
 the extremely simple and highly effective hardware but timing-critical
 design aspects of the circular loops in the 6600 were recognised by James
 Thornton (the co-designer of the 6600) as being paradoxically challenging
-to understand why so few gates could be so effective.  Consequently,
-documenting it just to be able to *develop* it is extremely important.
+to understand why so few gates could be so effective (being as they were,
+literally the world's first ever out-of-order superscalar architecture).
+Consequently, documenting it just to be able to *develop* it is extremely
+important.
 
 We're getting to the point where we need to connect the LOAD/STORE Computation
 Units up to an actual memory architecture.  We've chosen
@@ -413,9 +415,10 @@ from both Mitch Alsup and Staf Verhaegen.
 
 (Staf is also [sponsored by NLNet](https://nlnet.nl/project/Chips4Makers/)
 to create Libre-licensed Cell Libraries, busting through one of the -
-many - layers of NDAs and reducing NREs for ASIC development: I helped him
-put in the submission, and he was really happy to do the Cell Libraries
-that we will be using for LibreSOC's 180nm test tape-out in October 2020.)
+many - layers of NDAs and reducing NREs and unnecessary and artificial
+barriers for ASIC development: I helped him put in the submission, and
+he was really happy to do the Cell Libraries that we will be using for
+LibreSOC's 180nm test tape-out in October 2020.)
 
 # Public-Inbox and Domain Migration