-these discussions, what they fail to mention is that there are
-*multiple single-line* source wires, thus achieving the exact
-same purpose as the Reorder Buffer's CAM, with *far less power
-and die area*.
+these discussions (not being part of the patent), what they fail to
+mention is that there are *multiple single-line* source wires, thus
+achieving the exact same purpose as the Reorder Buffer's CAM, with *far
+less power and die area*.
+
+Mitch's description of this on comp.arch was that the Dependency Matrix columns
+effectively may be viewed as a single-bit-wide "CAM", which of course
+is far less hardware, being just AND gates. However it wasn't until
+he very kindly sent me the chapters of his unpublished book on the 6600
+that the significance of what he was saying actually sank in, namely that
+instead of a merged multi-wire very expensive "Destination Register" CAM,
+copying the *value* of the dependent src register into the Reorder Buffer
+(and then having to match it up afterwards. on every clock cycle),
+the Dependency Matrix breaks this down into multiple really really simple
+single wire comparators that *preserve* a **direct** link between the
+src register(s) and the destination(s) where they're needed. Consequently,
+the Scoreboard and Dependency Matrix logic gates take up far less space,
+and use significantly less power.