add summary update

diff --git a/updates/015_2019feb15_summary.mdwn b/updates/015_2019feb15_summary.mdwn
index 6f85730b6bfad320ecbc37950cecc32a3b82ce44..e6d9dfb8cc5d13f0e4a5292a8f75c6c9c3543d32 100644 (file)
--- a/updates/015_2019feb15_summary.mdwn
+++ b/updates/015_2019feb15_summary.mdwn
@@ -35,6 +35,15 @@ and denormalisation, as well as the packing and unpacking stages: they're all
 absolutely identical.  Consequently we can abstract these stages out into
 base classes.
 
+Also, an aside: many thanks to attie from #m-labs on Freenode: it turns
+out that converting verilog to migen as a way to learn is something that
+other people do as well.  It's a nice coincidence that attie
+converted the
+[milkymist FPU](https://github.com/m-labs/milkymist/blob/master/cores/pfpu/rtl/pfpu_faddsub.v) over to
+[migen](https://github.com/nakengelhardt/fpgagraphlib/blob/master/src/faddsub.py)
+as a way to avoid having to learn both migen as well as IEEE754.
+We'll be comparing notes :)
+
 # Virtual Memory / TLB
 
 A [TLB](https://en.wikipedia.org/wiki/Translation_lookaside_buffer)