complete coriolis2 section

diff --git a/updates/023_2020mar26_decoder_emulator_started.mdwn b/updates/023_2020mar26_decoder_emulator_started.mdwn
index 502882cb896a2b9e08ee3c24373fa1307139021b..80273084cea3c9f8e91d87b254459cd373aebb31 100644 (file)
--- a/updates/023_2020mar26_decoder_emulator_started.mdwn
+++ b/updates/023_2020mar26_decoder_emulator_started.mdwn
@@ -149,7 +149,22 @@ level hierarchy.
 
 [Explaining this](http://bugs.libre-riscv.org/show_bug.cgi?id=178#c146)
 to Jean-Paul was amusing and challenging.  Much bashing of heads against
-walls and keyboards was involved.  
+walls and keyboards was involved.  The basic plan: rather than have
+coriolis2 perform an *entire* layout, in a flat and all-or-nothing fashion,
+we need a much more subtle fine-grained approach, where *sub-blocks* are
+laid-out, then *included* at a given level of hierarchy as "pre-done blocks".
+
+Save and repeat.
+
+This apparently had never been done before, and explaining it in words was
+extremely challenging.  Through a massive hack (actively editing the underlying
+HDL files temporarily in between tasks) was the only way to illustrate it.
+However once the lightbulb went on, Jean-Paul was able to get coriolis2's
+c++ code into shape extremely rapidly, and this alone has opened up an
+*entire new avenue* of potential for coriolis2 to be used in industry
+for doing much larger ASICs.  Which is precisely the kind of thing that
+our NLNet sponsors (and the EU, from the Horizon 2020 Grant) love.  hooray.
+Now if only we could actually go to a conference and talk about it.
 
 # POWER ISA decoder and Simulator