fpga/u500vc707devkit/src/sdio.v

   1 // See LICENSE for license details.
   2 `timescale 1ns/1ps
   3 `default_nettype none
   4
   5 module sdio_spi_bridge (
   6   input wire clk,
   7   input wire reset,
   8   // SDIO
   9   inout  wire       sd_cmd,
  10   inout  wire [3:0] sd_dat,
  11   output wire       sd_sck,
  12   // QUAD SPI
  13   input  wire       spi_sck,
  14   input  wire [3:0] spi_dq_o,
  15   output wire [3:0] spi_dq_i,
  16   output wire       spi_cs
  17 );
  18
  19   wire mosi, miso;
  20   reg miso_sync [1:0];
  21
  22   assign mosi = spi_dq_o[0];
  23   assign spi_dq_i = {2'b00, miso_sync[1], 1'b0};
  24
  25   assign sd_sck = spi_sck;
  26
  27   IOBUF buf_cmd (
  28     .IO(sd_cmd),
  29     .I(mosi),
  30     .O(),
  31     .T(1'b0)
  32   );
  33
  34   IOBUF buf_dat0 (
  35     .IO(sd_dat[0]),
  36     .I(),
  37     .O(miso),
  38     .T(1'b1)
  39   );
  40
  41   IOBUF buf_dat3 (
  42     .IO(sd_dat[3]),
  43     .I(spi_cs),
  44     .O(),
  45     .T(1'b0)
  46   );
  47
  48   always @(posedge clk) begin
  49     if (reset) begin
  50        miso_sync[0] <= 1'b0;
  51        miso_sync[1] <= 1'b0;
  52     end else begin
  53        miso_sync[0] <= miso;
  54        miso_sync[1] <= miso_sync[0];
  55     end
  56   end
  57 endmodule
  58
  59 `default_nettype wire