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README: Updates to build bootloaders
author
Shreesha Srinath
<shreesha@csl.cornell.edu>
Sun, 20 Aug 2017 08:39:45 +0000
(
01:39
-0700)
committer
Shreesha Srinath
<shreesha@csl.cornell.edu>
Sun, 20 Aug 2017 08:39:45 +0000
(
01:39
-0700)
README.md
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b/README.md
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README.md
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README.md
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-13,15
+13,24
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Both systems boot autonomously and can be controlled via an external debugger.
Please read the section corresponding to the kit you are interested in for
instructions on how to use this repo.
Please read the section corresponding to the kit you are interested in for
instructions on how to use this repo.
+Software Requirement
+--------------------
-Freedom E310 Arty FPGA Dev Kit
+To compile the bootloaders for both Freedom E300 Arty and U500 VC707
+FPGA dev kits, the RISC-V software toolchain must be installed locally and
+set the $(RISCV) environment variable to point to the location of where the
+RISC-V toolchains are installed. You can build the toolchain from scratch
+or download the tools here: https://www.sifive.com/products/tools/
+
+
+Freedom E300 Arty FPGA Dev Kit
------------------------------
------------------------------
-The Freedom E3
10 Arty FPGA Dev Kit implements a Freedom E31
0 chip.
+The Freedom E3
00 Arty FPGA Dev Kit implements a Freedom E30
0 chip.
### How to build
### How to build
-The Makefile corresponding to the Freedom E3
1
0 Arty FPGA Dev Kit is
+The Makefile corresponding to the Freedom E3
0
0 Arty FPGA Dev Kit is
`Makefile.e300artydevkit` and it consists of two main targets:
- `verilog`: to compile the Chisel source files and generate the Verilog files.
`Makefile.e300artydevkit` and it consists of two main targets:
- `verilog`: to compile the Chisel source files and generate the Verilog files.