5df5ea7cb4db309b0c91465f027158c6f78598c3
[ieee754fpu.git] / src / ieee754 / fpcommon / pack.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Elaboratable
6 from nmigen.cli import main, verilog
7
8 from ieee754.fpcommon.fpbase import FPNumOut, FPNumBaseRecord, FPNumBase
9 from ieee754.fpcommon.fpbase import FPState
10 from .roundz import FPRoundData
11 from nmutil.singlepipe import Object
12 from ieee754.fpcommon.getop import FPBaseData
13
14
15 class FPPackData(Object):
16
17 def __init__(self, width, pspec):
18 Object.__init__(self)
19 self.z = Signal(width, reset_less=True) # result
20 self.ctx = FPBaseData(width, pspec)
21 self.mid = self.ctx.mid
22
23 class FPPackMod(Elaboratable):
24
25 def __init__(self, width, pspec):
26 self.width = width
27 self.pspec = pspec
28 self.i = self.ispec()
29 self.o = self.ospec()
30
31 def ispec(self):
32 return FPRoundData(self.width, self.pspec)
33
34 def ospec(self):
35 return FPPackData(self.width, self.pspec)
36
37 def process(self, i):
38 return self.o
39
40 def setup(self, m, in_z):
41 """ links module to inputs and outputs
42 """
43 m.submodules.pack = self
44 m.d.comb += self.i.eq(in_z)
45
46 def elaborate(self, platform):
47 m = Module()
48 z = FPNumBaseRecord(self.width, False)
49 m.submodules.pack_in_z = in_z = FPNumBase(self.i.z)
50 #m.submodules.pack_out_z = out_z = FPNumOut(z)
51 m.d.comb += self.o.ctx.eq(self.i.ctx)
52 with m.If(~self.i.out_do_z):
53 with m.If(in_z.is_overflowed):
54 m.d.comb += z.inf(self.i.z.s)
55 with m.Else():
56 m.d.comb += z.create(self.i.z.s, self.i.z.e, self.i.z.m)
57 with m.Else():
58 m.d.comb += z.v.eq(self.i.oz)
59 m.d.comb += self.o.z.eq(z.v)
60 return m
61
62
63 class FPPack(FPState):
64
65 def __init__(self, width, id_wid):
66 FPState.__init__(self, "pack")
67 self.mod = FPPackMod(width)
68 self.out_z = self.ospec()
69
70 def ispec(self):
71 return self.mod.ispec()
72
73 def ospec(self):
74 return self.mod.ospec()
75
76 def setup(self, m, in_z):
77 """ links module to inputs and outputs
78 """
79 self.mod.setup(m, in_z)
80
81 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
82 m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
83
84 def action(self, m):
85 m.next = "pack_put_z"