1b54db47294a2fe021e62301113a93b3df6e3147
1 """IEEE Floating Point Divider
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
6 from nmigen
import Module
, Signal
, Elaboratable
7 from nmigen
.cli
import main
, verilog
9 from ieee754
.fpcommon
.fpbase
import FPState
10 from ieee754
.fpcommon
.postcalc
import FPAddStage1Data
11 from .div0
import FPDivStage0Data
14 class FPDivStage2Mod(FPState
, Elaboratable
):
15 """ Second stage of div: preparation for normalisation.
18 def __init__(self
, width
, id_wid
):
25 return FPDivStage0Data(self
.width
, self
.id_wid
) # Q/Rem in...
28 return FPAddStage1Data(self
.width
, self
.id_wid
) # out to post-process
33 def setup(self
, m
, i
):
34 """ links module to inputs and outputs
36 m
.submodules
.div1
= self
37 #m.submodules.div1_out_overflow = self.o.of
39 m
.d
.comb
+= self
.i
.eq(i
)
41 def elaborate(self
, platform
):
44 # copies sign and exponent and mantissa (mantissa to be overridden
46 m
.d
.comb
+= self
.o
.z
.eq(self
.i
.z
)
48 # TODO: this is "phase 3" of divide (the very end of the pipeline)
49 # takes the Q and R data (whatever) and performs
50 # last-stage guard/round/sticky and copies mantissa into z.
51 # post-processing stages take care of things from that point.
53 # NOTE: this phase does NOT do ACTUAL DIV processing, it ONLY
54 # does "conversion" *out* of the Q/REM last stage
56 with m
.If(~self
.i
.out_do_z
):
59 self
.o
.z
.m
.eq(self
.i
.product
[mw
+2:]),
60 self
.o
.of
.m0
.eq(self
.i
.product
[mw
+2]),
61 self
.o
.of
.guard
.eq(self
.i
.product
[mw
+1]),
62 self
.o
.of
.round_bit
.eq(self
.i
.product
[mw
]),
63 self
.o
.of
.sticky
.eq(self
.i
.product
[0:mw
].bool())
66 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
67 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
68 m
.d
.comb
+= self
.o
.mid
.eq(self
.i
.mid
)
73 class FPDivStage2(FPState
):
75 def __init__(self
, width
, id_wid
):
76 FPState
.__init
__(self
, "divider_1")
77 self
.mod
= FPDivStage2Mod(width
)
78 self
.out_z
= FPNumBaseRecord(width
, False)
79 self
.out_of
= Overflow()
80 self
.norm_stb
= Signal()
82 def setup(self
, m
, i
):
83 """ links module to inputs and outputs
87 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in div1 state
89 m
.d
.sync
+= self
.out_of
.eq(self
.mod
.out_of
)
90 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
91 m
.d
.sync
+= self
.norm_stb
.eq(1)
94 m
.next
= "normalise_1"