src/ieee754/fpdiv/div2.py

   1 """IEEE Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import FPState
  10 from ieee754.fpcommon.postcalc import FPAddStage1Data
  11 from .div0 import FPDivStage0Data
  12
  13
  14 class FPDivStage1Mod(FPState, Elaboratable):
  15     """ Second stage of div: preparation for normalisation.
  16     """
  17
  18     def __init__(self, width, id_wid):
  19         self.width = width
  20         self.id_wid = id_wid
  21         self.i = self.ispec()
  22         self.o = self.ospec()
  23
  24     def ispec(self):
  25         return FPDivStage0Data(self.width, self.id_wid)
  26
  27     def ospec(self):
  28         return FPAddStage1Data(self.width, self.id_wid)
  29
  30     def process(self, i):
  31         return self.o
  32
  33     def setup(self, m, i):
  34         """ links module to inputs and outputs
  35         """
  36         m.submodules.div1 = self
  37         #m.submodules.div1_out_overflow = self.o.of
  38
  39         m.d.comb += self.i.eq(i)
  40
  41     def elaborate(self, platform):
  42         m = Module()
  43
  44         # copies sign and exponent and mantissa (mantissa to be overridden
  45         # below)
  46         m.d.comb += self.o.z.eq(self.i.z)
  47
  48         # TODO: this is "phase 3" of divide (the very end of the pipeline)
  49         # takes the Q and R data (whatever) and performs
  50         # last-stage guard/round/sticky and copies mantissa into z.
  51         # post-processing stages take care of things from that point.
  52
  53         with m.If(~self.i.out_do_z):
  54             mw = self.o.z.m_width
  55             m.d.comb += [
  56                 self.o.z.m.eq(self.i.product[mw+2:]),
  57                 self.o.of.m0.eq(self.i.product[mw+2]),
  58                 self.o.of.guard.eq(self.i.product[mw+1]),
  59                 self.o.of.round_bit.eq(self.i.product[mw]),
  60                 self.o.of.sticky.eq(self.i.product[0:mw].bool())
  61             ]
  62
  63         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  64         m.d.comb += self.o.oz.eq(self.i.oz)
  65         m.d.comb += self.o.mid.eq(self.i.mid)
  66
  67         return m
  68
  69
  70 class FPDivStage1(FPState):
  71
  72     def __init__(self, width, id_wid):
  73         FPState.__init__(self, "divider_1")
  74         self.mod = FPDivStage1Mod(width)
  75         self.out_z = FPNumBaseRecord(width, False)
  76         self.out_of = Overflow()
  77         self.norm_stb = Signal()
  78
  79     def setup(self, m, i):
  80         """ links module to inputs and outputs
  81         """
  82         self.mod.setup(m, i)
  83
  84         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in div1 state
  85
  86         m.d.sync += self.out_of.eq(self.mod.out_of)
  87         m.d.sync += self.out_z.eq(self.mod.out_z)
  88         m.d.sync += self.norm_stb.eq(1)
  89
  90     def action(self, m):
  91         m.next = "normalise_1"
  92