15f1555d969098246dc9df4bf1f3ffce812d6958
[ieee754fpu.git] / src / ieee754 / fpsqrt / fsqrt.py
1 from sfpy import Float32
2
3
4 # XXX DO NOT USE, fails on num=65536. wark-wark...
5 def sqrtsimple(num):
6 res = 0
7 bit = 1
8
9 while (bit < num):
10 bit <<= 2
11
12 while (bit != 0):
13 if (num >= res + bit):
14 num -= res + bit
15 res = (res >> 1) + bit
16 else:
17 res >>= 1
18 bit >>= 2
19
20 return res
21
22
23 def sqrt(num):
24 D = num # D is input (from num)
25 Q = 0 # quotient
26 R = 0 # remainder
27 for i in range(64, -1, -1): # negative ranges are weird...
28
29 R = (R<<2)|((D>>(i+i))&3)
30
31 if R >= 0:
32 R -= ((Q<<2)|1) # -Q01
33 else:
34 R += ((Q<<2)|3) # +Q11
35
36 Q <<= 1
37 if R >= 0:
38 Q |= 1 # new Q
39
40 if R < 0:
41 R = R + ((Q<<1)|1)
42
43 return Q, R
44
45
46 # grabbed these from unit_test_single (convenience, this is just experimenting)
47
48 def get_mantissa(x):
49 return 0x7fffff & x
50
51 def get_exponent(x):
52 return ((x & 0x7f800000) >> 23) - 127
53
54 def set_exponent(x, e):
55 return (x & ~0x7f800000) | ((e+127) << 23)
56
57 def get_sign(x):
58 return ((x & 0x80000000) >> 31)
59
60 # convert FP32 to s/e/m
61 def create_fp32(s, e, m):
62 """ receive sign, exponent, mantissa, return FP32 """
63 return set_exponent((s << 31) | get_mantissa(m))
64
65 # convert s/e/m to FP32
66 def decode_fp32(x):
67 """ receive FP32, return sign, exponent, mantissa """
68 return get_sign(x), get_exponent(x), get_mantissa(x)
69
70
71 # main function, takes mantissa and exponent as separate arguments
72 # returns a tuple, sqrt'd mantissa, sqrt'd exponent
73
74 def main(mantissa, exponent):
75 if exponent & 1 != 0:
76 # shift mantissa up, subtract 1 from exp to compensate
77 mantissa <<= 1
78 exponent -= 1
79 m, r = sqrt(mantissa)
80 return m, r, exponent >> 1
81
82
83 #normalization function
84 def normalise(s, m, e, lowbits):
85 if (lowbits >= 2):
86 m += 1
87 if get_mantissa(m) == ((1<<24)-1):
88 e += 1
89 #if the num is NaN, than adjust
90 if (e == 128 & m !=0):
91 z[31] = 1
92 z[30:23] = 255
93 z[22] = 1
94 z[21:0] = 0
95 #if the num is Inf, then adjust
96 if (e == 128):
97 z[31] = s
98 z[30:23] = 255
99 z[22:0] = 0
100
101 return s, m, e
102
103
104 def fsqrt_test(x):
105
106 xbits = x.bits
107 print ("x", x, type(x))
108 sq_test = x.sqrt()
109 print ("sqrt", sq_test)
110
111 print (xbits, type(xbits))
112 s, e, m = decode_fp32(xbits)
113 print("x decode", s, e, m, hex(m))
114
115 m |= 1<<23 # set top bit (the missing "1" from mantissa)
116 m <<= 27
117
118 sm, sr, se = main(m, e)
119 lowbits = sm & 0x3
120 sm >>= 2
121 sm = get_mantissa(sm)
122 #sm += 2
123
124 s, sm, se = normalise(s, sm, se, lowbits)
125
126 print("our sqrt", s, se, sm, hex(sm), bin(sm), "lowbits", lowbits,
127 "rem", hex(sr))
128 if lowbits >= 2:
129 print ("probably needs rounding (+1 on mantissa)")
130
131 sq_xbits = sq_test.bits
132 s, e, m = decode_fp32(sq_xbits)
133 print ("sf32 sqrt", s, e, m, hex(m), bin(m))
134 print ()
135
136 if __name__ == '__main__':
137
138 # quick test up to 1000 of two sqrt functions
139 for Q in range(1, int(1e4)):
140 print(Q, sqrt(Q), sqrtsimple(Q), int(Q**0.5))
141 assert int(Q**0.5) == sqrtsimple(Q), "Q sqrtsimpl fail %d" % Q
142 assert int(Q**0.5) == sqrt(Q)[0], "Q sqrt fail %d" % Q
143
144 # quick mantissa/exponent demo
145 for e in range(26):
146 for m in range(26):
147 ms, mr, es = main(m, e)
148 print("m:%d e:%d sqrt: m:%d-%d e:%d" % (m, e, ms, mr, es))
149
150 x = Float32(1234.123456789)
151 fsqrt_test(x)
152 x = Float32(32.1)
153 fsqrt_test(x)
154 x = Float32(16.0)
155 fsqrt_test(x)
156 x = Float32(8.0)
157 fsqrt_test(x)
158 x = Float32(8.5)
159 fsqrt_test(x)
160 x = Float32(3.14159265358979323)
161 fsqrt_test(x)
162 x = Float32(12.99392923123123)
163 fsqrt_test(x)
164 x = Float32(0.123456)
165 fsqrt_test(x)
166
167
168
169
170 """
171
172 Notes:
173 https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf
174
175 //This is the main code of integer sqrt function found here:http://verilogcodes.blogspot.com/2017/11/a-verilog-function-for-finding-square-root.html
176 //
177
178 module testbench;
179
180 reg [15:0] sqr;
181
182 //Verilog function to find square root of a 32 bit number.
183 //The output is 16 bit.
184 function [15:0] sqrt;
185 input [31:0] num; //declare input
186 //intermediate signals.
187 reg [31:0] a;
188 reg [15:0] q;
189 reg [17:0] left,right,r;
190 integer i;
191 begin
192 //initialize all the variables.
193 a = num;
194 q = 0;
195 i = 0;
196 left = 0; //input to adder/sub
197 right = 0; //input to adder/sub
198 r = 0; //remainder
199 //run the calculations for 16 iterations.
200 for(i=0;i<16;i=i+1) begin
201 right = {q,r[17],1'b1};
202 left = {r[15:0],a[31:30]};
203 a = {a[29:0],2'b00}; //left shift by 2 bits.
204 if (r[17] == 1) //add if r is negative
205 r = left + right;
206 else //subtract if r is positive
207 r = left - right;
208 q = {q[14:0],!r[17]};
209 end
210 sqrt = q; //final assignment of output.
211 end
212 endfunction //end of Function
213
214
215 c version (from paper linked from URL)
216
217 unsigned squart(D, r) /*Non-Restoring sqrt*/
218 unsigned D; /*D:32-bit unsigned integer to be square rooted */
219 int *r;
220 {
221 unsigned Q = 0; /*Q:16-bit unsigned integer (root)*/
222 int R = 0; /*R:17-bit integer (remainder)*/
223 int i;
224 for (i = 15;i>=0;i--) /*for each root bit*/
225 {
226 if (R>=0)
227 { /*new remainder:*/
228 R = R<<2)|((D>>(i+i))&3);
229 R = R-((Q<<2)|1); /*-Q01*/
230 }
231 else
232 { /*new remainder:*/
233 R = R<<2)|((D>>(i+i))&3);
234 R = R+((Q<<2)|3); /*+Q11*/
235 }
236 if (R>=0) Q = Q<<1)|1; /*new Q:*/
237 else Q = Q<<1)|0; /*new Q:*/
238 }
239
240 /*remainder adjusting*/
241 if (R<0) R = R+((Q<<1)|1);
242 *r = R; /*return remainder*/
243 return(Q); /*return root*/
244 }
245
246 From wikipedia page:
247
248 short isqrt(short num) {
249 short res = 0;
250 short bit = 1 << 14; // The second-to-top bit is set: 1 << 30 for 32 bits
251
252 // "bit" starts at the highest power of four <= the argument.
253 while (bit > num)
254 bit >>= 2;
255
256 while (bit != 0) {
257 if (num >= res + bit) {
258 num -= res + bit;
259 res = (res >> 1) + bit;
260 }
261 else
262 res >>= 1;
263 bit >>= 2;
264 }
265 return res;
266 }
267
268 """