a300fb03bdd83d9ee5d010d75d76d88459daef2c
[ieee754fpu.git] / src / ieee754 / part_cmp / ripple.py
1 # need to ripple the starting LSB of each partition up through the
2 # rest of the partition. a Mux on the partition gate therefore selects
3 # either the current "thing" being propagated, or, if the gate is set open,
4 # will select the current bit from the input.
5 #
6 # this is actually a useful function, it's one of "set before first" or
7 # "set after first" from vector predication processing.
8
9 from nmigen import Signal, Module, Elaboratable, Mux
10
11
12 class RippleLSB(Elaboratable):
13 def __init__(self, width):
14 self.width = width
15 self.results_in = Signal(width, reset_less=True)
16 self.gates = Signal(width-1, reset_less=True)
17
18 self.output = Signal(width, reset_less=True)
19
20 def elaborate(self, platform):
21 m = Module()
22 comb = m.d.comb
23 width = self.width
24
25 current_result = self.results_in[0]
26 comb += self.output[0].eq(current_result)
27
28 for i in range(width-1):
29 cur = Signal(name="cur%d" % i)
30 comb += cur.eq(current_result)
31 current_result = Mux(self.gates[i], self.results_in[i+1], cur)
32 comb += self.output[i+1].eq(current_result)
33
34 return m