looking for replacements of the hard-coded control blocks

[ieee754fpu.git] / src / add / multipipe.py

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index e07818a7922739ac987ef93d41880899f7feaa9d..35da5c2ec741aafc66e97804e842be0395b8a863 100644 (file)
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -191,7 +191,9 @@ class CombMultiOutPipeline(MultiOutControlBase):
 
         # temporaries
         p_i_valid = Signal(reset_less=True)
-        m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
+        pv = Signal(reset_less=True)
+        m.d.comb += p_i_valid.eq(self.p.i_valid_test)
+        m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
 
         # all outputs to next stages first initialised to zero (invalid)
         # the only output "active" is then selected by the muxid
@@ -201,7 +203,7 @@ class CombMultiOutPipeline(MultiOutControlBase):
         m.d.comb += self.p.o_ready.eq(~data_valid | self.n[mid].i_ready)
         m.d.comb += data_valid.eq(p_i_valid | \
                                     (~self.n[mid].i_ready & data_valid))
-        with m.If(self.p.i_valid & self.p.o_ready):
+        with m.If(pv):
             m.d.comb += eq(r_data, self.p.i_data)
         m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))
 
@@ -258,6 +260,8 @@ class CombMultiInPipeline(MultiInControlBase):
             n_i_readyn = Array(n_i_readyn)
             data_valid = Array(data_valid)
 
+        nirn = Signal(reset_less=True)
+        m.d.comb += nirn.eq(~self.n.i_ready)
         mid = self.p_mux.m_id
         for i in range(p_len):
             m.d.comb += data_valid[i].eq(0)
@@ -266,7 +270,7 @@ class CombMultiInPipeline(MultiInControlBase):
             m.d.comb += self.p[i].o_ready.eq(0)
         m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
         m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
-        m.d.comb += n_i_readyn[mid].eq(~self.n.i_ready & data_valid[mid])
+        m.d.comb += n_i_readyn[mid].eq(nirn & data_valid[mid])
         anyvalid = Signal(i, reset_less=True)
         av = []
         for i in range(p_len):
@@ -319,7 +323,7 @@ class InputPriorityArbiter:
         in_ready = []
         for i in range(self.num_rows):
             p_i_valid = Signal(reset_less=True)
-            m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_logic())
+            m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_test)
             in_ready.append(p_i_valid)
         m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids"
         m.d.comb += self.active.eq(~pe.n)   # encoder active (one input valid)