# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
from nmigen.cli import main, verilog
from math import log
def __init__(self, width, id_wid):
self.z = FPOpOut(width)
self.z.data_o = Signal(width)
- self.mid = Signal(id_wid, reset_less=True)
+ self.muxid = Signal(id_wid, reset_less=True)
def __iter__(self):
yield self.z
- yield self.mid
+ yield self.muxid
def eq(self, i):
- return [self.z.eq(i.z), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.muxid.eq(i.mid)]
def ports(self):
return list(self)
-class FPADDBaseMod:
+class FPADDBaseMod(Elaboratable):
def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
""" IEEE754 FP Add
get.trigger_setup(m, self.in_t.stb, self.in_t.ack)
chainlist = [get, sc, alm, n1]
- chain = StageChain(chainlist, specallocate=True)
+ chain = StageChain(chainlist, specallocate=False)
chain.setup(m, self.i)
m.submodules.sc = sc
m.submodules.alm = alm
m.d.sync += self.out_z.stb.eq(1)
-class FPADD(FPID):
+class FPADD(FPID, Elaboratable):
""" FPADD: stages as follows:
FPGetOp (a)