big convert g/s/r mid --> muxid

[ieee754fpu.git] / src / ieee754 / fpadd / statemachine.py

diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py
index bdcec1ba266f38cca97a1931befeca47c77969a4..decbc3d4e87f58630df8afe797d03398a186e857 100644 (file)
--- a/src/ieee754/fpadd/statemachine.py
+++ b/src/ieee754/fpadd/statemachine.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
@@ -33,20 +33,20 @@ class FPOpData:
     def __init__(self, width, id_wid):
         self.z = FPOpOut(width)
         self.z.data_o = Signal(width)
-        self.mid = Signal(id_wid, reset_less=True)
+        self.muxid = Signal(id_wid, reset_less=True)
 
     def __iter__(self):
         yield self.z
-        yield self.mid
+        yield self.muxid
 
     def eq(self, i):
-        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+        return [self.z.eq(i.z), self.muxid.eq(i.mid)]
 
     def ports(self):
         return list(self)
 
 
-class FPADDBaseMod:
+class FPADDBaseMod(Elaboratable):
 
     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
         """ IEEE754 FP Add
@@ -107,9 +107,11 @@ class FPADDBaseMod:
 
         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
         sc.setup(m, a, b, self.in_mid)
+        m.submodules.sc = sc
 
         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
         dn.setup(m, a, b, sc.in_mid)
+        m.submodules.dn = dn
 
         if self.single_cycle:
             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
@@ -117,12 +119,15 @@ class FPADDBaseMod:
         else:
             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
+        m.submodules.alm = alm
 
         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
+        m.submodules.add0 = add0
 
         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
+        m.submodules.add1 = add1
 
         if self.single_cycle:
             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
@@ -156,11 +161,14 @@ class FPADDBaseMod:
         get.trigger_setup(m, self.in_t.stb, self.in_t.ack)
 
         chainlist = [get, sc, alm, n1]
-        chain = StageChain(chainlist, specallocate=True)
+        chain = StageChain(chainlist, specallocate=False)
         chain.setup(m, self.i)
+        m.submodules.sc = sc
+        m.submodules.alm = alm
+        m.submodules.n1 = n1
 
         for mod in chainlist:
-            sc = self.add_state(mod)
+            self.add_state(mod)
 
         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
                                     n1.out_z.mid, self.o.mid))
@@ -260,7 +268,7 @@ class FPADDBase(FPState):
                 m.d.sync += self.out_z.stb.eq(1)
 
 
-class FPADD(FPID):
+class FPADD(FPID, Elaboratable):
     """ FPADD: stages as follows:
 
         FPGetOp (a)