big convert g/s/r mid --> muxid

[ieee754fpu.git] / src / ieee754 / fpcommon / pack.py

diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py
index 1464883cdeec57ed4fcc002ecb192b557f7db4fc..37ab1ecad89f19618ec76e70c92d44ff7c94b8cf 100644 (file)
--- a/src/ieee754/fpcommon/pack.py
+++ b/src/ieee754/fpcommon/pack.py
@@ -5,33 +5,34 @@
 from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumOut
-from fpbase import FPState
-from fpcommon.roundz import FPRoundData
-from singlepipe import Object
+from ieee754.fpcommon.fpbase import FPNumOut, FPNumBaseRecord, FPNumBase
+from ieee754.fpcommon.fpbase import FPState
+from .roundz import FPRoundData
+from nmutil.singlepipe import Object
+from ieee754.fpcommon.getop import FPBaseData
 
 
 class FPPackData(Object):
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         Object.__init__(self)
-        self.z = Signal(width, reset_less=True)
-        self.mid = Signal(id_wid, reset_less=True)
-
+        self.z = Signal(width, reset_less=True)    # result
+        self.ctx = FPBaseData(width, pspec)
+        self.muxid = self.ctx.muxid
 
 class FPPackMod(Elaboratable):
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         self.width = width
-        self.id_wid = id_wid
+        self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPRoundData(self.width, self.id_wid)
+        return FPRoundData(self.width, self.pspec)
 
     def ospec(self):
-        return FPPackData(self.width, self.id_wid)
+        return FPPackData(self.width, self.pspec)
 
     def process(self, i):
         return self.o
@@ -44,12 +45,12 @@ class FPPackMod(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        z = FPNumOut(self.width, False)
-        m.submodules.pack_in_z = self.i.z
-        m.submodules.pack_out_z = z
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        z = FPNumBaseRecord(self.width, False)
+        m.submodules.pack_in_z = in_z = FPNumBase(self.i.z)
+        #m.submodules.pack_out_z = out_z = FPNumOut(z)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
         with m.If(~self.i.out_do_z):
-            with m.If(self.i.z.is_overflowed):
+            with m.If(in_z.is_overflowed):
                 m.d.comb += z.inf(self.i.z.s)
             with m.Else():
                 m.d.comb += z.create(self.i.z.s, self.i.z.e, self.i.z.m)
@@ -78,7 +79,7 @@ class FPPack(FPState):
         self.mod.setup(m, in_z)
 
         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
-        m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
+        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
 
     def action(self, m):
         m.next = "pack_put_z"