rework roundz to use Mux

[ieee754fpu.git] / src / ieee754 / fpcommon / roundz.py

diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index 1585b310934f43d057e658573b82eba22147d126..88795fbe3adab2e4653547ac6d45a1cfd6937d2c 100644 (file)
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -2,20 +2,20 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal, Mux
 from nmigen.cli import main, verilog
 
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
-from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.getop import FPPipeContext
-from .postnormalise import FPNorm1Data
+from ieee754.fpcommon.postnormalise import FPNorm1Data
 
 
 class FPRoundData:
 
     def __init__(self, pspec):
-        width = pspec['width']
-        self.z = FPNumBaseRecord(width, False)
+        width = pspec.width
+        self.z = FPNumBaseRecord(width, False, name="z")
         self.ctx = FPPipeContext(pspec)
         self.muxid = self.ctx.muxid
         # pipeline bypass [data comes from specialcases]
@@ -24,16 +24,14 @@ class FPRoundData:
 
     def eq(self, i):
         ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.ctx.eq(i.ctx)]
+               self.ctx.eq(i.ctx)]
         return ret
 
 
-class FPRoundMod(Elaboratable):
+class FPRoundMod(PipeModBase):
 
     def __init__(self, pspec):
-        self.pspec = pspec
-        self.i = self.ispec()
-        self.out_z = self.ospec()
+        super().__init__(pspec, "roundz")
 
     def ispec(self):
         return FPNorm1Data(self.pspec)
@@ -41,46 +39,16 @@ class FPRoundMod(Elaboratable):
     def ospec(self):
         return FPRoundData(self.pspec)
 
-    def process(self, i):
-        return self.out_z
-
-    def setup(self, m, i):
-        m.submodules.roundz = self
-        m.d.comb += self.i.eq(i)
-
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
-        with m.If(~self.i.out_do_z): # bypass wasn't enabled
-            with m.If(self.i.roundz):
-                m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
-                with m.If(self.i.z.m == self.i.z.m1s): # all 1s
-                    m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
-
-        return m
+        comb = m.d.comb
 
+        comb += self.o.eq(self.i)  # copies muxid, z, out_do_z
+        im = self.i.z.m
+        ie = self.i.z.e
+        msb1s = Signal(reset_less=True)
+        comb += msb1s.eq(~(~self.i.z.m).bool())  # all 1s
+        comb += self.o.z.m.eq(Mux(self.i.roundz, im+1, im))  # mantissa up
+        comb += self.o.z.e.eq(Mux(msb1s & self.i.roundz, ie + 1, ie)) # exp up
 
-class FPRound(FPState):
-
-    def __init__(self, width, id_wid):
-        FPState.__init__(self, "round")
-        self.mod = FPRoundMod(width)
-        self.out_z = self.ospec()
-
-    def ispec(self):
-        return self.mod.ispec()
-
-    def ospec(self):
-        return self.mod.ospec()
-
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        self.mod.setup(m, i)
-
-        self.idsync(m)
-        m.d.sync += self.out_z.eq(self.mod.out_z)
-        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
-
-    def action(self, m):
-        m.next = "corrections"
+        return m