add f8 fma tests -- f16 takes >8hr to run with bitwuzla

[ieee754fpu.git] / src / ieee754 / fpfma / main_stage.py

diff --git a/src/ieee754/fpfma/main_stage.py b/src/ieee754/fpfma/main_stage.py
index 7a028107e40d1c52ae363b42019b2c550f91e91f..5823ffe8f1b86a2634e807c74421005b85af8533 100644 (file)
--- a/src/ieee754/fpfma/main_stage.py
+++ b/src/ieee754/fpfma/main_stage.py
@@ -4,18 +4,18 @@ computes `z = (a * c) + b` but only rounds once at the end
 """
 
 from nmutil.pipemodbase import PipeModBase, PipeModBaseChain
-from ieee754.fpcommon.fpbase import FPRoundingMode
+from ieee754.fpcommon.fpbase import FPRoundingMode, FPFormat
 from ieee754.fpfma.special_cases import FPFMASpecialCasesDeNormOutData
 from nmigen.hdl.dsl import Module
 from nmigen.hdl.ast import Signal, signed, unsigned, Mux, Cat
 from ieee754.fpfma.util import expanded_exponent_shape, \
-    expanded_mantissa_shape, get_fpformat, EXPANDED_MANTISSA_EXTRA_LSBS
+    expanded_mantissa_shape, EXPANDED_MANTISSA_EXTRA_LSBS
 from ieee754.fpcommon.getop import FPPipeContext
 
 
 class FPFMAPostCalcData:
     def __init__(self, pspec):
-        fpf = get_fpformat(pspec)
+        fpf = FPFormat.from_pspec(pspec)
 
         self.sign = Signal()
         """sign"""
@@ -74,7 +74,7 @@ class FPFMAMain(PipeModBase):
 
     def elaborate(self, platform):
         m = Module()
-        fpf = get_fpformat(self.pspec)
+        fpf = FPFormat.from_pspec(self.pspec)
         assert fpf.has_sign
         inp = self.i
         out = self.o