Use RipleLSB in PartitionedXOR, and invert outputs

[ieee754fpu.git] / src / ieee754 / part / formal / proof_partition.py

diff --git a/src/ieee754/part/formal/proof_partition.py b/src/ieee754/part/formal/proof_partition.py
index 5867cdb931f358d0ebe16fbbf4fc96bce26d27d3..c8181153289b945232746aa25dea9bd6980afeaf 100644 (file)
--- a/src/ieee754/part/formal/proof_partition.py
+++ b/src/ieee754/part/formal/proof_partition.py
@@ -568,7 +568,8 @@ class PartitionTestCase(FHDLTestCase):
         def op_xor(obj):
             return obj.xor()
 
-        module = ComparisonOpDriver(op_xor, nops=1)
+        # 8-bit partitions take a long time, for some reason
+        module = ComparisonOpDriver(op_xor, nops=1, width=32, mwidth=4)
         self.assertFormal(module, mode="bmc", depth=1)