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[ieee754fpu.git] / src / ieee754 / part_cmp / gt_combiner.py

diff --git a/src/ieee754/part_cmp/gt_combiner.py b/src/ieee754/part_cmp/gt_combiner.py
index 2828cd16d1311f63ac0b8cf7e9e72b7345efb65d..05082028cdf8f5d9b68482d2182b59a4d9a5f113 100644 (file)
--- a/src/ieee754/part_cmp/gt_combiner.py
+++ b/src/ieee754/part_cmp/gt_combiner.py
@@ -1,5 +1,5 @@
 from nmigen import Signal, Module, Elaboratable, Mux
-from ieee754.part_mul_add.partpoints import PartitionPoints
+
 
 class Combiner(Elaboratable):
 
@@ -28,6 +28,7 @@ class Combiner(Elaboratable):
 # equal flag is set AND the previous partition's greater than output
 # is true
 
+
 class GTCombiner(Elaboratable):
 
     def __init__(self, width):
@@ -46,8 +47,8 @@ class GTCombiner(Elaboratable):
         self.aux_input = Signal(reset_less=True)  # right hand side mux input
         self.gt_en = Signal(reset_less=True)      # enable or disable gt signal
 
-        self.eqs = Signal(width, reset_less=True) # the flags for EQ
-        self.gts = Signal(width, reset_less=True) # the flags for GT
+        self.eqs = Signal(width, reset_less=True)  # the flags for EQ
+        self.gts = Signal(width, reset_less=True)  # the flags for GT
         self.gates = Signal(width-1, reset_less=True)
         self.outputs = Signal(width, reset_less=True)