run tests in parallel

[ieee754fpu.git] / src / ieee754 / part_mul_add / adder.py

diff --git a/src/ieee754/part_mul_add/adder.py b/src/ieee754/part_mul_add/adder.py
index 2eb6de27e868b8f1f3be78604400361a70561760..e1849b4d25fc5ec4fc4473cc02b32f49dd5912b2 100644 (file)
--- a/src/ieee754/part_mul_add/adder.py
+++ b/src/ieee754/part_mul_add/adder.py
@@ -134,7 +134,7 @@ class PartitionedAdder(Elaboratable):
     exp-o    : o....oN...oN...oN...oN...x (32+4+2 bits - x to be discarded)
     o        :  .... N... N... N... N... (32 bits - x ignored, N is carry-over)
     carry-out: o    o    o    o    o      (5 bits)
-    
+
     A couple of differences should be noted:
      - The expanded a/b/o have 2 extra bits added to them. These bits
        allow the carry-in for the least significant partition to be
@@ -149,7 +149,7 @@ class PartitionedAdder(Elaboratable):
        to extract the carry-out information for each partition, as
        when there is a carry out in a partition, the next most
        significant partition bit will be set to 1
-    
+
     Additionally, the carry-out bits must be rearranged before being
     output to move the most significant carry bit for each partition
     into the least significant bit for that partition, as well as to
@@ -261,8 +261,13 @@ class PartitionedAdder(Elaboratable):
         # special hardware on FPGAs
         comb += expanded_o.eq(expanded_a + expanded_b)
 
+        # ok now we have the carry-out, however because it's the MSB it's
+        # in the wrong position in the output as far as putting it into
+        # a chain of adds (or other operations).  therefore we need to
+        # "ripple" carry-out down to the same position that carry-in is
+        # in [the LSB of each partition].
         comb += ripple.results_in.eq(carry_tmp)
         comb += ripple.gates.eq(self.part_pts.as_sig())
-        comb += self.carry_out.eq(ripple.output)
+        m.d.sync += self.carry_out.eq(ripple.output)
 
         return m