return False
return True
+ def part_byte(self, index, mfactor=1): # mfactor used for "expanding"
+ if index == -1 or index == 7:
+ return C(True, 1)
+ assert index >= 0 and index < 8
+ return self[(index * 8 + 8)*mfactor]
+
class FullAdder(Elaboratable):
"""Full Adder.
return m
+class Parts(Elaboratable):
+
+ def __init__(self, pbwid, epps, n_parts):
+ self.pbwid = pbwid
+ # inputs
+ self.epps = PartitionPoints.like(epps, name="epps") # expanded points
+ # outputs
+ self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+
+ def elaborate(self, platform):
+ m = Module()
+
+ epps, parts = self.epps, self.parts
+ # collect part-bytes (double factor because the input is extended)
+ pbs = Signal(self.pbwid, reset_less=True)
+ tl = []
+ for i in range(self.pbwid):
+ pb = Signal(name="pb%d" % i, reset_less=True)
+ m.d.comb += pb.eq(epps.part_byte(i, mfactor=2)) # double
+ tl.append(pb)
+ m.d.comb += pbs.eq(Cat(*tl))
+
+ # negated-temporary copy of partition bits
+ npbs = Signal.like(pbs, reset_less=True)
+ m.d.comb += npbs.eq(~pbs)
+ byte_count = 8 // len(parts)
+ for i in range(len(parts)):
+ pbl = []
+ pbl.append(npbs[i * byte_count - 1])
+ for j in range(i * byte_count, (i + 1) * byte_count - 1):
+ pbl.append(pbs[j])
+ pbl.append(npbs[(i + 1) * byte_count - 1])
+ value = Signal(len(pbl), name="value_%d" % i, reset_less=True)
+ m.d.comb += value.eq(Cat(*pbl))
+ m.d.comb += parts[i].eq(~(value).bool())
+
+ return m
+
+
class Part(Elaboratable):
""" a key class which, depending on the partitioning, will determine
what action to take when parts of the output are signed or unsigned.
def __init__(self, width, out_wid, n_parts):
self.width = width
self.n_parts = n_parts
- self.delayed_part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
+ self.part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
for i in range(8)]
self.intermed = Signal(out_wid, reset_less=True)
self.output = Signal(out_wid//2, reset_less=True)
for i in range(self.n_parts):
op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
m.d.comb += op.eq(
- Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
+ Mux(self.part_ops[sel * i] == OP_MUL_LOW,
self.intermed.part(i * w*2, w),
self.intermed.part(i * w*2 + w, w)))
ol.append(op)
# output
self.output = Signal(64)
- def _part_byte(self, index):
- if index == -1 or index == 7:
- return C(True, 1)
- assert index >= 0 and index < 8
- return self.part_pts[index * 8 + 8]
-
def elaborate(self, platform):
m = Module()
tl = []
for i in range(8):
pb = Signal(name="pb%d" % i, reset_less=True)
- m.d.comb += pb.eq(self._part_byte(i))
+ m.d.comb += pb.eq(self.part_pts.part_byte(i))
tl.append(pb)
m.d.comb += pbs.eq(Cat(*tl))
+ # create (doubled) PartitionPoints (output is double input width)
+ expanded_part_pts = PartitionPoints()
+ for i, v in self.part_pts.items():
+ ep = Signal(name=f"expanded_part_pts_{i*2}", reset_less=True)
+ expanded_part_pts[i * 2] = ep
+ m.d.comb += ep.eq(v)
+
# local variables
signs = []
for i in range(8):
m.d.comb += mod.orin[i].eq(l[i])
terms.append(mod.orout)
- expanded_part_pts = PartitionPoints()
- for i, v in self.part_pts.items():
- signal = Signal(name=f"expanded_part_pts_{i*2}", reset_less=True)
- expanded_part_pts[i * 2] = signal
- m.d.comb += signal.eq(v)
-
add_reduce = AddReduce(terms,
128,
self.register_levels,
m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
m.d.comb += io64.intermed.eq(self._intermediate_output)
for i in range(8):
- m.d.comb += io64.delayed_part_ops[i].eq(out_part_ops[i])
+ m.d.comb += io64.part_ops[i].eq(out_part_ops[i])
# create _output_32
m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
m.d.comb += io32.intermed.eq(self._intermediate_output)
for i in range(8):
- m.d.comb += io32.delayed_part_ops[i].eq(out_part_ops[i])
+ m.d.comb += io32.part_ops[i].eq(out_part_ops[i])
# create _output_16
m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
m.d.comb += io16.intermed.eq(self._intermediate_output)
for i in range(8):
- m.d.comb += io16.delayed_part_ops[i].eq(out_part_ops[i])
+ m.d.comb += io16.part_ops[i].eq(out_part_ops[i])
# create _output_8
m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
m.d.comb += io8.intermed.eq(self._intermediate_output)
for i in range(8):
- m.d.comb += io8.delayed_part_ops[i].eq(out_part_ops[i])
+ m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
# final output
m.submodules.finalout = finalout = FinalOut(64)
projects / ieee754fpu.git / blobdiff