rename inputs to not include []

[ieee754fpu.git] / src / ieee754 / part_mul_add / multiply.py

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 010897b54305337f09afe814554ec0a3f76365e0..6f770842f8aa048c6afc2b8e54b5013f2e91e985 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -301,7 +301,7 @@ class AddReduceData:
     def __init__(self, ppoints, n_inputs, output_width, n_parts):
         self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
                           for i in range(n_parts)]
-        self.inputs = [Signal(output_width, name=f"inputs[{i}]",
+        self.inputs = [Signal(output_width, name=f"inputs_{i}",
                               reset_less=True)
                         for i in range(n_inputs)]
         self.reg_partition_points = ppoints.like()
@@ -569,6 +569,9 @@ class AddReduce(Elaboratable):
         inputs = self.inputs
         ilen = len(inputs)
         while True:
+            groups = AddReduceSingle.full_adder_groups(len(inputs))
+            if len(groups) == 0:
+                break
             next_level = AddReduceSingle(ilen, self.output_width, n_parts,
                                          next_levels, partition_points)
             mods.append(next_level)
@@ -577,9 +580,6 @@ class AddReduce(Elaboratable):
             inputs = next_level.o.inputs
             ilen = len(inputs)
             part_ops = next_level.i.part_ops
-            groups = AddReduceSingle.full_adder_groups(len(inputs))
-            if len(groups) == 0:
-                break
 
         next_level = FinalAdd(ilen, self.output_width, n_parts,
                               next_levels, partition_points)