rename inputs to not include []

[ieee754fpu.git] / src / ieee754 / part_mul_add / multiply.py

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index b03284ad2ccfee40d8ef678232b1896485b64cde..6f770842f8aa048c6afc2b8e54b5013f2e91e985 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -234,9 +234,9 @@ class PartitionedAdder(Elaboratable):
         :param partition_points: the input partition points
         """
         self.width = width
-        self.a = Signal(width)
-        self.b = Signal(width)
-        self.output = Signal(width)
+        self.a = Signal(width, reset_less=True)
+        self.b = Signal(width, reset_less=True)
+        self.output = Signal(width, reset_less=True)
         self.partition_points = PartitionPoints(partition_points)
         if not self.partition_points.fits_in_width(width):
             raise ValueError("partition_points doesn't fit in width")
@@ -301,8 +301,9 @@ class AddReduceData:
     def __init__(self, ppoints, n_inputs, output_width, n_parts):
         self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
                           for i in range(n_parts)]
-        self.inputs = [Signal(output_width, name=f"inputs[{i}]", reset_less=True)
-            for i in range(n_inputs)]
+        self.inputs = [Signal(output_width, name=f"inputs_{i}",
+                              reset_less=True)
+                        for i in range(n_inputs)]
         self.reg_partition_points = ppoints.like()
 
     def eq_from(self, reg_partition_points, inputs, part_ops):
@@ -568,6 +569,9 @@ class AddReduce(Elaboratable):
         inputs = self.inputs
         ilen = len(inputs)
         while True:
+            groups = AddReduceSingle.full_adder_groups(len(inputs))
+            if len(groups) == 0:
+                break
             next_level = AddReduceSingle(ilen, self.output_width, n_parts,
                                          next_levels, partition_points)
             mods.append(next_level)
@@ -576,9 +580,6 @@ class AddReduce(Elaboratable):
             inputs = next_level.o.inputs
             ilen = len(inputs)
             part_ops = next_level.i.part_ops
-            groups = AddReduceSingle.full_adder_groups(len(inputs))
-            if len(groups) == 0:
-                break
 
         next_level = FinalAdd(ilen, self.output_width, n_parts,
                               next_levels, partition_points)
@@ -832,19 +833,22 @@ class Part(Elaboratable):
         self.epps = epps
 
         # inputs
-        self.a = Signal(64)
-        self.b = Signal(64)
-        self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
-        self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+        self.a = Signal(64, reset_less=True)
+        self.b = Signal(64, reset_less=True)
+        self.a_signed = [Signal(name=f"a_signed_{i}", reset_less=True)
+                            for i in range(8)]
+        self.b_signed = [Signal(name=f"_b_signed_{i}", reset_less=True)
+                            for i in range(8)]
         self.pbs = Signal(pbwid, reset_less=True)
 
         # outputs
-        self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+        self.parts = [Signal(name=f"part_{i}", reset_less=True)
+                            for i in range(n_parts)]
 
-        self.not_a_term = Signal(width)
-        self.neg_lsb_a_term = Signal(width)
-        self.not_b_term = Signal(width)
-        self.neg_lsb_b_term = Signal(width)
+        self.not_a_term = Signal(width, reset_less=True)
+        self.neg_lsb_a_term = Signal(width, reset_less=True)
+        self.not_b_term = Signal(width, reset_less=True)
+        self.neg_lsb_b_term = Signal(width, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
@@ -1055,7 +1059,7 @@ class Mul8_16_32_64(Elaboratable):
         self.b = Signal(64)
 
         # intermediates (needed for unit tests)
-        self._intermediate_output = Signal(128)
+        self.intermediate_output = Signal(128)
 
         # output
         self.output = Signal(64)
@@ -1142,28 +1146,28 @@ class Mul8_16_32_64(Elaboratable):
         out_part_pts = add_reduce.o.reg_partition_points
 
         m.submodules.add_reduce = add_reduce
-        m.d.comb += self._intermediate_output.eq(add_reduce.o.output)
+        m.d.comb += self.intermediate_output.eq(add_reduce.o.output)
         # create _output_64
         m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
-        m.d.comb += io64.intermed.eq(self._intermediate_output)
+        m.d.comb += io64.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io64.part_ops[i].eq(out_part_ops[i])
 
         # create _output_32
         m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
-        m.d.comb += io32.intermed.eq(self._intermediate_output)
+        m.d.comb += io32.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io32.part_ops[i].eq(out_part_ops[i])
 
         # create _output_16
         m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
-        m.d.comb += io16.intermed.eq(self._intermediate_output)
+        m.d.comb += io16.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io16.part_ops[i].eq(out_part_ops[i])
 
         # create _output_8
         m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
-        m.d.comb += io8.intermed.eq(self._intermediate_output)
+        m.d.comb += io8.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
 
@@ -1198,7 +1202,7 @@ if __name__ == "__main__":
     m = Mul8_16_32_64()
     main(m, ports=[m.a,
                    m.b,
-                   m._intermediate_output,
+                   m.intermediate_output,
                    m.output,
                    *m.part_ops,
                    *m.part_pts.values()])