:param width: the bit width of the input and output
"""
- self.in0 = Signal(width)
- self.in1 = Signal(width)
- self.in2 = Signal(width)
- self.sum = Signal(width)
- self.carry = Signal(width)
+ self.in0 = Signal(width, reset_less=True)
+ self.in1 = Signal(width, reset_less=True)
+ self.in2 = Signal(width, reset_less=True)
+ self.sum = Signal(width, reset_less=True)
+ self.carry = Signal(width, reset_less=True)
def elaborate(self, platform):
"""Elaborate this module."""
:param partition_points: the input partition points
"""
self.width = width
- self.a = Signal(width)
- self.b = Signal(width)
- self.output = Signal(width)
+ self.a = Signal(width, reset_less=True)
+ self.b = Signal(width, reset_less=True)
+ self.output = Signal(width, reset_less=True)
self.partition_points = PartitionPoints(partition_points)
if not self.partition_points.fits_in_width(width):
raise ValueError("partition_points doesn't fit in width")
expanded_width += 1
expanded_width += 1
self._expanded_width = expanded_width
- # XXX these have to remain here due to some horrible nmigen
- # simulation bugs involving sync. it is *not* necessary to
- # have them here, they should (under normal circumstances)
- # be moved into elaborate, as they are entirely local
- self._expanded_a = Signal(expanded_width) # includes extra part-points
- self._expanded_b = Signal(expanded_width) # likewise.
- self._expanded_o = Signal(expanded_width) # likewise.
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
+ expanded_a = Signal(self._expanded_width, reset_less=True)
+ expanded_b = Signal(self._expanded_width, reset_less=True)
+ expanded_o = Signal(self._expanded_width, reset_less=True)
+
expanded_index = 0
# store bits in a list, use Cat later. graphviz is much cleaner
al, bl, ol, ea, eb, eo = [],[],[],[],[],[]
if i in self.partition_points:
# add extra bit set to 0 + 0 for enabled partition points
# and 1 + 0 for disabled partition points
- ea.append(self._expanded_a[expanded_index])
+ ea.append(expanded_a[expanded_index])
al.append(~self.partition_points[i]) # add extra bit in a
- eb.append(self._expanded_b[expanded_index])
+ eb.append(expanded_b[expanded_index])
bl.append(C(0)) # yes, add a zero
expanded_index += 1 # skip the extra point. NOT in the output
- ea.append(self._expanded_a[expanded_index])
- eb.append(self._expanded_b[expanded_index])
- eo.append(self._expanded_o[expanded_index])
+ ea.append(expanded_a[expanded_index])
+ eb.append(expanded_b[expanded_index])
+ eo.append(expanded_o[expanded_index])
al.append(self.a[i])
bl.append(self.b[i])
ol.append(self.output[i])
# use only one addition to take advantage of look-ahead carry and
# special hardware on FPGAs
- m.d.comb += self._expanded_o.eq(
- self._expanded_a + self._expanded_b)
+ m.d.comb += expanded_o.eq(expanded_a + expanded_b)
return m
class AddReduceData:
def __init__(self, ppoints, n_inputs, output_width, n_parts):
- self.part_ops = [Signal(2, name=f"part_ops_{i}")
+ self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
for i in range(n_parts)]
- self.inputs = [Signal(output_width, name=f"inputs[{i}]")
- for i in range(n_inputs)]
+ self.inputs = [Signal(output_width, name=f"inputs_{i}",
+ reset_less=True)
+ for i in range(n_inputs)]
self.reg_partition_points = ppoints.like()
def eq_from(self, reg_partition_points, inputs, part_ops):
class FinalReduceData:
def __init__(self, ppoints, output_width, n_parts):
- self.part_ops = [Signal(2, name=f"part_ops_{i}")
+ self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
for i in range(n_parts)]
- self.output = Signal(output_width)
+ self.output = Signal(output_width, reset_less=True)
self.reg_partition_points = ppoints.like()
def eq_from(self, reg_partition_points, output, part_ops):
m = Module()
output_width = self.output_width
- output = Signal(output_width)
+ output = Signal(output_width, reset_less=True)
if self.n_inputs == 0:
# use 0 as the default output value
m.d.comb += output.eq(0)
# etc because this is not in elaboratable.
self.groups = AddReduceSingle.full_adder_groups(n_inputs)
self._intermediate_terms = []
+ self.adders = []
if len(self.groups) != 0:
self.create_next_terms()
for i in range(len(self.i.part_ops))]
# set up the partition mask (for the adders)
+ part_mask = Signal(self.output_width, reset_less=True)
+
mask = self.i.reg_partition_points.as_mask(self.output_width)
- m.d.comb += self.part_mask.eq(mask)
+ m.d.comb += part_mask.eq(mask)
# add and link the intermediate term modules
for i, (iidx, adder_i) in enumerate(self.adders):
m.d.comb += adder_i.in0.eq(self.i.inputs[iidx])
m.d.comb += adder_i.in1.eq(self.i.inputs[iidx + 1])
m.d.comb += adder_i.in2.eq(self.i.inputs[iidx + 2])
- m.d.comb += adder_i.mask.eq(self.part_mask)
+ m.d.comb += adder_i.mask.eq(part_mask)
return m
def add_intermediate_term(value):
_intermediate_terms.append(value)
- # store mask in intermediary (simplifies graph)
- self.part_mask = Signal(self.output_width, reset_less=True)
-
# create full adders for this recursive level.
# this shrinks N terms to 2 * (N // 3) plus the remainder
- self.adders = []
for i in self.groups:
adder_i = MaskedFullAdder(self.output_width)
self.adders.append((i, adder_i))
"""
self.inputs = inputs
self.part_ops = part_ops
- self.out_part_ops = [Signal(2, name=f"out_part_ops_{i}")
- for i in range(len(part_ops))]
- self.output = Signal(output_width)
+ n_parts = len(part_ops)
+ self.o = FinalReduceData(partition_points, output_width, n_parts)
self.output_width = output_width
self.register_levels = register_levels
self.partition_points = partition_points
inputs = self.inputs
ilen = len(inputs)
while True:
+ groups = AddReduceSingle.full_adder_groups(len(inputs))
+ if len(groups) == 0:
+ break
next_level = AddReduceSingle(ilen, self.output_width, n_parts,
next_levels, partition_points)
mods.append(next_level)
inputs = next_level.o.inputs
ilen = len(inputs)
part_ops = next_level.i.part_ops
- groups = AddReduceSingle.full_adder_groups(len(inputs))
- if len(groups) == 0:
- break
- if ilen != 0:
- next_level = FinalAdd(ilen, self.output_width, n_parts,
- next_levels, partition_points)
- mods.append(next_level)
+ next_level = FinalAdd(ilen, self.output_width, n_parts,
+ next_levels, partition_points)
+ mods.append(next_level)
self.levels = mods
i = mcur.o # for next loop
# output comes from last module
- m.d.comb += self.output.eq(i.output)
- copy_part_ops = [self.out_part_ops[idx].eq(i.part_ops[idx])
- for idx in range(len(self.part_ops))]
- m.d.comb += copy_part_ops
+ m.d.comb += self.o.eq(i)
return m
# inputs
self.epps = PartitionPoints.like(epps, name="epps") # expanded points
# outputs
- self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+ self.parts = [Signal(name=f"part_{i}", reset_less=True)
+ for i in range(n_parts)]
def elaborate(self, platform):
m = Module()
self.epps = epps
# inputs
- self.a = Signal(64)
- self.b = Signal(64)
- self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
- self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.a = Signal(64, reset_less=True)
+ self.b = Signal(64, reset_less=True)
+ self.a_signed = [Signal(name=f"a_signed_{i}", reset_less=True)
+ for i in range(8)]
+ self.b_signed = [Signal(name=f"_b_signed_{i}", reset_less=True)
+ for i in range(8)]
self.pbs = Signal(pbwid, reset_less=True)
# outputs
- self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+ self.parts = [Signal(name=f"part_{i}", reset_less=True)
+ for i in range(n_parts)]
- self.not_a_term = Signal(width)
- self.neg_lsb_a_term = Signal(width)
- self.not_b_term = Signal(width)
- self.neg_lsb_b_term = Signal(width)
+ self.not_a_term = Signal(width, reset_less=True)
+ self.neg_lsb_a_term = Signal(width, reset_less=True)
+ self.not_b_term = Signal(width, reset_less=True)
+ self.neg_lsb_b_term = Signal(width, reset_less=True)
def elaborate(self, platform):
m = Module()
self.b = Signal(64)
# intermediates (needed for unit tests)
- self._intermediate_output = Signal(128)
+ self.intermediate_output = Signal(128)
# output
self.output = Signal(64)
expanded_part_pts,
self.part_ops)
- out_part_ops = add_reduce.out_part_ops
- out_part_pts = add_reduce.levels[-1].o.reg_partition_points
+ out_part_ops = add_reduce.o.part_ops
+ out_part_pts = add_reduce.o.reg_partition_points
m.submodules.add_reduce = add_reduce
- m.d.comb += self._intermediate_output.eq(add_reduce.output)
+ m.d.comb += self.intermediate_output.eq(add_reduce.o.output)
# create _output_64
m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
- m.d.comb += io64.intermed.eq(self._intermediate_output)
+ m.d.comb += io64.intermed.eq(self.intermediate_output)
for i in range(8):
m.d.comb += io64.part_ops[i].eq(out_part_ops[i])
# create _output_32
m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
- m.d.comb += io32.intermed.eq(self._intermediate_output)
+ m.d.comb += io32.intermed.eq(self.intermediate_output)
for i in range(8):
m.d.comb += io32.part_ops[i].eq(out_part_ops[i])
# create _output_16
m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
- m.d.comb += io16.intermed.eq(self._intermediate_output)
+ m.d.comb += io16.intermed.eq(self.intermediate_output)
for i in range(8):
m.d.comb += io16.part_ops[i].eq(out_part_ops[i])
# create _output_8
m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
- m.d.comb += io8.intermed.eq(self._intermediate_output)
+ m.d.comb += io8.intermed.eq(self.intermediate_output)
for i in range(8):
m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
m = Mul8_16_32_64()
main(m, ports=[m.a,
m.b,
- m._intermediate_output,
+ m.intermediate_output,
m.output,
*m.part_ops,
*m.part_pts.values()])
projects / ieee754fpu.git / blobdiff