from nmigen.cli import main
from functools import reduce
from operator import or_
+from ieee754.pipeline import PipelineSpec
+from nmutil.pipemodbase import PipeModBase
class PartitionPoints(dict):
""" Final stage of add reduce
"""
- def __init__(self, n_inputs, output_width, n_parts, partition_points,
+ def __init__(self, lidx, n_inputs, output_width, n_parts, partition_points,
partition_step=1):
+ self.lidx = lidx
self.partition_step = partition_step
self.output_width = output_width
self.n_inputs = n_inputs
return FinalReduceData(self.partition_points,
self.output_width, self.n_parts)
+ def setup(self, m, i):
+ m.submodules.finaladd = self
+ m.d.comb += self.i.eq(i)
+
+ def process(self, i):
+ return self.o
+
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
supported, except for by ``Signal.eq``.
"""
- def __init__(self, n_inputs, output_width, n_parts, partition_points,
+ def __init__(self, lidx, n_inputs, output_width, n_parts, partition_points,
partition_step=1):
"""Create an ``AddReduce``.
:param output_width: bit-width of ``output``.
:param partition_points: the input partition points.
"""
+ self.lidx = lidx
self.partition_step = partition_step
self.n_inputs = n_inputs
self.n_parts = n_parts
return AddReduceData(self.partition_points, self.n_terms,
self.output_width, self.n_parts)
+ def setup(self, m, i):
+ setattr(m.submodules, "addreduce_%d" % self.lidx, self)
+ m.d.comb += self.i.eq(i)
+
+ def process(self, i):
+ return self.o
+
@staticmethod
def calc_n_inputs(n_inputs, groups):
retval = len(groups)*2
groups = AddReduceSingle.full_adder_groups(len(inputs))
if len(groups) == 0:
break
- next_level = AddReduceSingle(ilen, self.output_width, n_parts,
+ lidx = len(mods)
+ next_level = AddReduceSingle(lidx, ilen, self.output_width, n_parts,
partition_points,
self.partition_step)
mods.append(next_level)
ilen = len(inputs)
part_ops = next_level.i.part_ops
- next_level = FinalAdd(ilen, self.output_width, n_parts,
+ lidx = len(mods)
+ next_level = FinalAdd(lidx, ilen, self.output_width, n_parts,
partition_points, self.partition_step)
mods.append(next_level)
the extra terms - as separate terms - are then thrown at the
AddReduce alongside the multiplication part-results.
"""
- def __init__(self, part_pts, width, n_parts, n_levels, pbwid):
+ def __init__(self, part_pts, width, n_parts, pbwid):
self.pbwid = pbwid
self.part_pts = part_pts
def ospec(self):
return OutputData()
+ def setup(self, m, i):
+ m.submodules.finalout = self
+ m.d.comb += self.i.eq(i)
+
+ def process(self, i):
+ return self.o
+
def elaborate(self, platform):
m = Module()
self.output.eq(rhs.output)]
-class AllTerms(Elaboratable):
+class AllTerms(PipeModBase):
"""Set of terms to be added together
"""
- def __init__(self, n_inputs, output_width, n_parts, register_levels):
- """Create an ``AddReduce``.
-
- :param inputs: input ``Signal``s to be summed.
- :param output_width: bit-width of ``output``.
- :param register_levels: List of nesting levels that should have
- pipeline registers.
- :param partition_points: the input partition points.
+ def __init__(self, pspec):
+ """Create an ``AllTerms``.
"""
- self.register_levels = register_levels
- self.n_inputs = n_inputs
- self.n_parts = n_parts
- self.output_width = output_width
-
- self.i = self.ispec()
- self.o = self.ospec()
+ self.n_inputs = pspec.n_inputs
+ self.n_parts = pspec.n_parts
+ self.output_width = pspec.width
+ super().__init__(pspec, "allterms")
def ispec(self):
return InputData()
setattr(m.submodules, "signs%d" % i, s)
m.d.comb += s.part_ops.eq(self.i.part_ops[i])
- n_levels = len(self.register_levels)+1
- m.submodules.part_8 = part_8 = Part(eps, 128, 8, n_levels, 8)
- m.submodules.part_16 = part_16 = Part(eps, 128, 4, n_levels, 8)
- m.submodules.part_32 = part_32 = Part(eps, 128, 2, n_levels, 8)
- m.submodules.part_64 = part_64 = Part(eps, 128, 1, n_levels, 8)
+ m.submodules.part_8 = part_8 = Part(eps, 128, 8, 8)
+ m.submodules.part_16 = part_16 = Part(eps, 128, 4, 8)
+ m.submodules.part_32 = part_32 = Part(eps, 128, 2, 8)
+ m.submodules.part_64 = part_64 = Part(eps, 128, 1, 8)
nat_l, nbt_l, nla_l, nlb_l = [], [], [], []
for mod in [part_8, part_16, part_32, part_64]:
m.d.comb += mod.a.eq(self.i.a)
def ospec(self):
return IntermediateData(self.part_pts, self.output_width, self.n_parts)
+ def setup(self, m, i):
+ m.submodules.intermediates = self
+ m.d.comb += self.i.eq(i)
+
+ def process(self, i):
+ return self.o
+
def elaborate(self, platform):
m = Module()
flip-flops are to be inserted.
"""
+ self.id_wid = 0 # num_bits(num_rows)
+ self.op_wid = 0
+ self.pspec = PipelineSpec(128, self.id_wid, self.op_wid, n_ops=3)
+ self.pspec.n_inputs = 64 + 4
+ self.pspec.n_parts = 8
+
# parameter(s)
self.register_levels = list(register_levels)
part_pts = self.part_pts
- n_inputs = 64 + 4
- n_parts = 8
- t = AllTerms(n_inputs, 128, n_parts, self.register_levels)
- m.submodules.allterms = t
- m.d.comb += t.i.eq(self.i)
+ n_parts = self.pspec.n_parts
+ n_inputs = self.pspec.n_inputs
+ output_width = self.pspec.width
+ t = AllTerms(self.pspec)
+ t.setup(m, self.i)
terms = t.o.terms
- at = AddReduceInternal(t.o, 128, partition_step=2)
+ at = AddReduceInternal(t.process(self.i), 128, partition_step=2)
i = at.i
for idx in range(len(at.levels)):
mcur = at.levels[idx]
- setattr(m.submodules, "addreduce_%d" % idx, mcur)
+ mcur.setup(m, i)
+ o = mcur.ospec()
if idx in self.register_levels:
- m.d.sync += mcur.i.eq(i)
+ m.d.sync += o.eq(mcur.process(i))
else:
- m.d.comb += mcur.i.eq(i)
- i = mcur.o # for next loop
+ m.d.comb += o.eq(mcur.process(i))
+ i = o # for next loop
interm = Intermediates(128, 8, part_pts)
- m.submodules.intermediates = interm
- m.d.comb += interm.i.eq(i)
+ interm.setup(m, i)
+ o = interm.process(interm.i)
# final output
- m.submodules.finalout = finalout = FinalOut(128, 8, part_pts)
- m.d.comb += finalout.i.eq(interm.o)
- m.d.comb += self.o.eq(finalout.o)
+ finalout = FinalOut(128, 8, part_pts)
+ finalout.setup(m, o)
+ m.d.comb += self.o.eq(finalout.process(o))
return m