remove need to pass register_levels to AddReduceSingle

[ieee754fpu.git] / src / ieee754 / part_mul_add / multiply.py

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 672bbfd33acdef4510167e6ec1d8c78e0bf3603f..92afc2bbd85f18e6305a7f85576af793d2d8e2af 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -616,7 +616,7 @@ class AddReduce(Elaboratable):
         m.d.comb += i.eq_from(partition_points, inputs, part_ops)
         for idx in range(len(self.levels)):
             mcur = self.levels[idx]
-            if 0 in mcur.register_levels:
+            if idx in self.register_levels:
                 m.d.sync += mcur.i.eq(i)
             else:
                 m.d.comb += mcur.i.eq(i)