move part_mask

[ieee754fpu.git] / src / ieee754 / part_mul_add / multiply.py

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index e0fe069d5b44139b12373fbfec72849d1396d813..a67f4b4ccf7b8aed40f204a5d64159d17888e7e9 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -427,6 +427,7 @@ class AddReduceSingle(Elaboratable):
         # etc because this is not in elaboratable.
         self.groups = AddReduceSingle.full_adder_groups(n_inputs)
         self._intermediate_terms = []
+        self.adders = []
         if len(self.groups) != 0:
             self.create_next_terms()
 
@@ -470,8 +471,10 @@ class AddReduceSingle(Elaboratable):
                                      for i in range(len(self.i.part_ops))]
 
         # set up the partition mask (for the adders)
+        part_mask = Signal(self.output_width, reset_less=True)
+
         mask = self.i.reg_partition_points.as_mask(self.output_width)
-        m.d.comb += self.part_mask.eq(mask)
+        m.d.comb += part_mask.eq(mask)
 
         # add and link the intermediate term modules
         for i, (iidx, adder_i) in enumerate(self.adders):
@@ -480,7 +483,7 @@ class AddReduceSingle(Elaboratable):
             m.d.comb += adder_i.in0.eq(self.i.inputs[iidx])
             m.d.comb += adder_i.in1.eq(self.i.inputs[iidx + 1])
             m.d.comb += adder_i.in2.eq(self.i.inputs[iidx + 2])
-            m.d.comb += adder_i.mask.eq(self.part_mask)
+            m.d.comb += adder_i.mask.eq(part_mask)
 
         return m
 
@@ -491,12 +494,8 @@ class AddReduceSingle(Elaboratable):
         def add_intermediate_term(value):
             _intermediate_terms.append(value)
 
-        # store mask in intermediary (simplifies graph)
-        self.part_mask = Signal(self.output_width, reset_less=True)
-
         # create full adders for this recursive level.
         # this shrinks N terms to 2 * (N // 3) plus the remainder
-        self.adders = []
         for i in self.groups:
             adder_i = MaskedFullAdder(self.output_width)
             self.adders.append((i, adder_i))
@@ -543,9 +542,8 @@ class AddReduce(Elaboratable):
         """
         self.inputs = inputs
         self.part_ops = part_ops
-        self.out_part_ops = [Signal(2, name=f"out_part_ops_{i}")
-                          for i in range(len(part_ops))]
-        self.output = Signal(output_width)
+        n_parts = len(part_ops)
+        self.o = FinalReduceData(partition_points, output_width, n_parts)
         self.output_width = output_width
         self.register_levels = register_levels
         self.partition_points = partition_points
@@ -586,10 +584,9 @@ class AddReduce(Elaboratable):
             if len(groups) == 0:
                 break
 
-        if ilen != 0:
-            next_level = FinalAdd(ilen, self.output_width, n_parts,
-                                  next_levels, partition_points)
-            mods.append(next_level)
+        next_level = FinalAdd(ilen, self.output_width, n_parts,
+                              next_levels, partition_points)
+        mods.append(next_level)
 
         self.levels = mods
 
@@ -617,10 +614,7 @@ class AddReduce(Elaboratable):
             i = mcur.o # for next loop
 
         # output comes from last module
-        m.d.comb += self.output.eq(i.output)
-        copy_part_ops = [self.out_part_ops[idx].eq(i.part_ops[idx])
-                                     for idx in range(len(self.part_ops))]
-        m.d.comb += copy_part_ops
+        m.d.comb += self.o.eq(i)
 
         return m
 
@@ -1147,11 +1141,11 @@ class Mul8_16_32_64(Elaboratable):
                                expanded_part_pts,
                                self.part_ops)
 
-        out_part_ops = add_reduce.out_part_ops
-        out_part_pts = add_reduce.levels[-1].o.reg_partition_points
+        out_part_ops = add_reduce.o.part_ops
+        out_part_pts = add_reduce.o.reg_partition_points
 
         m.submodules.add_reduce = add_reduce
-        m.d.comb += self._intermediate_output.eq(add_reduce.output)
+        m.d.comb += self._intermediate_output.eq(add_reduce.o.output)
         # create _output_64
         m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
         m.d.comb += io64.intermed.eq(self._intermediate_output)