""" Final stage of add reduce
"""
- def __init__(self, n_inputs, output_width, n_parts, partition_points):
- self.i = AddReduceData(partition_points, n_inputs,
- output_width, n_parts)
- self.o = FinalReduceData(partition_points, output_width, n_parts)
+ def __init__(self, n_inputs, output_width, n_parts, partition_points,
+ partition_step=1):
+ self.partition_step = partition_step
self.output_width = output_width
self.n_inputs = n_inputs
self.n_parts = n_parts
if not self.partition_points.fits_in_width(output_width):
raise ValueError("partition_points doesn't fit in output_width")
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return AddReduceData(self.partition_points, self.n_inputs,
+ self.output_width, self.n_parts)
+
+ def ospec(self):
+ return FinalReduceData(self.partition_points,
+ self.output_width, self.n_parts)
+
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
# base case for adding 2 inputs
assert self.n_inputs == 2
adder = PartitionedAdder(output_width,
- self.i.part_pts, 2)
+ self.i.part_pts, self.partition_step)
m.submodules.final_adder = adder
m.d.comb += adder.a.eq(self.i.terms[0])
m.d.comb += adder.b.eq(self.i.terms[1])
self.n_inputs = n_inputs
self.n_parts = n_parts
self.output_width = output_width
- self.i = AddReduceData(partition_points, n_inputs,
- output_width, n_parts)
self.partition_points = PartitionPoints(partition_points)
if not self.partition_points.fits_in_width(output_width):
raise ValueError("partition_points doesn't fit in output_width")
self.groups = AddReduceSingle.full_adder_groups(n_inputs)
- n_terms = AddReduceSingle.calc_n_inputs(n_inputs, self.groups)
- self.o = AddReduceData(partition_points, n_terms, output_width, n_parts)
+ self.n_terms = AddReduceSingle.calc_n_inputs(n_inputs, self.groups)
+
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return AddReduceData(self.partition_points, self.n_inputs,
+ self.output_width, self.n_parts)
+
+ def ospec(self):
+ return AddReduceData(self.partition_points, self.n_terms,
+ self.output_width, self.n_parts)
@staticmethod
def calc_n_inputs(n_inputs, groups):
return m
-class AddReduce(Elaboratable):
+class AddReduceInternal:
"""Recursively Add list of numbers together.
:attribute inputs: input ``Signal``s to be summed. Modification not
supported, except for by ``Signal.eq``.
"""
- def __init__(self, inputs, output_width, register_levels, partition_points,
- part_ops):
+ def __init__(self, i, output_width, partition_step=1):
"""Create an ``AddReduce``.
:param inputs: input ``Signal``s to be summed.
:param output_width: bit-width of ``output``.
- :param register_levels: List of nesting levels that should have
- pipeline registers.
:param partition_points: the input partition points.
"""
- self.inputs = inputs
- self.part_ops = part_ops
- n_parts = len(part_ops)
- self.o = FinalReduceData(partition_points, output_width, n_parts)
+ self.i = i
+ self.inputs = i.terms
+ self.part_ops = i.part_ops
self.output_width = output_width
- self.register_levels = register_levels
- self.partition_points = partition_points
+ self.partition_points = i.part_pts
+ self.partition_step = partition_step
self.create_levels()
- @staticmethod
- def get_max_level(input_count):
- return AddReduceSingle.get_max_level(input_count)
-
- @staticmethod
- def next_register_levels(register_levels):
- """``Iterable`` of ``register_levels`` for next recursive level."""
- for level in register_levels:
- if level > 0:
- yield level - 1
-
def create_levels(self):
"""creates reduction levels"""
part_ops = next_level.i.part_ops
next_level = FinalAdd(ilen, self.output_width, n_parts,
- partition_points)
+ partition_points, self.partition_step)
mods.append(next_level)
self.levels = mods
+
+class AddReduce(AddReduceInternal, Elaboratable):
+ """Recursively Add list of numbers together.
+
+ :attribute inputs: input ``Signal``s to be summed. Modification not
+ supported, except for by ``Signal.eq``.
+ :attribute register_levels: List of nesting levels that should have
+ pipeline registers.
+ :attribute output: output sum.
+ :attribute partition_points: the input partition points. Modification not
+ supported, except for by ``Signal.eq``.
+ """
+
+ def __init__(self, inputs, output_width, register_levels, part_pts,
+ part_ops, partition_step=1):
+ """Create an ``AddReduce``.
+
+ :param inputs: input ``Signal``s to be summed.
+ :param output_width: bit-width of ``output``.
+ :param register_levels: List of nesting levels that should have
+ pipeline registers.
+ :param partition_points: the input partition points.
+ """
+ self._inputs = inputs
+ self._part_pts = part_pts
+ self._part_ops = part_ops
+ n_parts = len(part_ops)
+ self.i = AddReduceData(part_pts, len(inputs),
+ output_width, n_parts)
+ AddReduceInternal.__init__(self, self.i, output_width, partition_step)
+ self.o = FinalReduceData(part_pts, output_width, n_parts)
+ self.register_levels = register_levels
+
+ @staticmethod
+ def get_max_level(input_count):
+ return AddReduceSingle.get_max_level(input_count)
+
+ @staticmethod
+ def next_register_levels(register_levels):
+ """``Iterable`` of ``register_levels`` for next recursive level."""
+ for level in register_levels:
+ if level > 0:
+ yield level - 1
+
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
+ m.d.comb += self.i.eq_from(self._part_pts, self._inputs, self._part_ops)
+
for i, next_level in enumerate(self.levels):
setattr(m.submodules, "next_level%d" % i, next_level)
- partition_points = self.partition_points
- inputs = self.inputs
- part_ops = self.part_ops
- n_parts = len(part_ops)
- n_inputs = len(inputs)
- output_width = self.output_width
- i = AddReduceData(partition_points, n_inputs, output_width, n_parts)
- m.d.comb += i.eq_from(partition_points, inputs, part_ops)
+ i = self.i
for idx in range(len(self.levels)):
mcur = self.levels[idx]
if idx in self.register_levels:
bsb = Signal(self.width, reset_less=True)
a_index, b_index = self.a_index, self.b_index
pwidth = self.pwidth
- m.d.comb += bsa.eq(self.a.part(a_index * pwidth, pwidth))
- m.d.comb += bsb.eq(self.b.part(b_index * pwidth, pwidth))
+ m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
m.d.comb += self.ti.eq(bsa * bsb)
m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
"""
asel = Signal(width, reset_less=True)
bsel = Signal(width, reset_less=True)
a_index, b_index = self.a_index, self.b_index
- m.d.comb += asel.eq(self.a.part(a_index * pwidth, pwidth))
- m.d.comb += bsel.eq(self.b.part(b_index * pwidth, pwidth))
+ m.d.comb += asel.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsel.eq(self.b.bit_select(b_index * pwidth, pwidth))
m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled))
m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled))
m.d.comb += self.ti.eq(bsa * bsb)
pa = LSBNegTerm(bit_wid)
setattr(m.submodules, "lnt_%d_a_%d" % (bit_wid, i), pa)
m.d.comb += pa.part.eq(parts[i])
- m.d.comb += pa.op.eq(self.a.part(bit_wid * i, bit_wid))
+ m.d.comb += pa.op.eq(self.a.bit_select(bit_wid * i, bit_wid))
m.d.comb += pa.signed.eq(self.b_signed[i * byte_width]) # yes b
m.d.comb += pa.msb.eq(self.b[(i + 1) * bit_wid - 1]) # really, b
nat.append(pa.nt)
pb = LSBNegTerm(bit_wid)
setattr(m.submodules, "lnt_%d_b_%d" % (bit_wid, i), pb)
m.d.comb += pb.part.eq(parts[i])
- m.d.comb += pb.op.eq(self.b.part(bit_wid * i, bit_wid))
+ m.d.comb += pb.op.eq(self.b.bit_select(bit_wid * i, bit_wid))
m.d.comb += pb.signed.eq(self.a_signed[i * byte_width]) # yes a
m.d.comb += pb.msb.eq(self.a[(i + 1) * bit_wid - 1]) # really, a
nbt.append(pb.nt)
op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
m.d.comb += op.eq(
Mux(self.part_ops[sel * i] == OP_MUL_LOW,
- self.intermed.part(i * w*2, w),
- self.intermed.part(i * w*2 + w, w)))
+ self.intermed.bit_select(i * w*2, w),
+ self.intermed.bit_select(i * w*2 + w, w)))
ol.append(op)
m.d.comb += self.output.eq(Cat(*ol))
"""
def __init__(self, output_width, n_parts, part_pts):
self.part_pts = part_pts
- self.i = IntermediateData(part_pts, output_width, n_parts)
+ self.output_width = output_width
+ self.n_parts = n_parts
self.out_wid = output_width//2
- # output
- self.out = Signal(self.out_wid, reset_less=True)
- self.intermediate_output = Signal(output_width, reset_less=True)
+
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return IntermediateData(self.part_pts, self.output_width, self.n_parts)
+
+ def ospec(self):
+ return OutputData()
def elaborate(self, platform):
m = Module()
op = Signal(8, reset_less=True, name="op_%d" % i)
m.d.comb += op.eq(
Mux(d8[i] | d16[i // 2],
- Mux(d8[i], i8.part(i * 8, 8), i16.part(i * 8, 8)),
- Mux(d32[i // 4], i32.part(i * 8, 8), i64.part(i * 8, 8))))
+ Mux(d8[i], i8.bit_select(i * 8, 8),
+ i16.bit_select(i * 8, 8)),
+ Mux(d32[i // 4], i32.bit_select(i * 8, 8),
+ i64.bit_select(i * 8, 8))))
ol.append(op)
- m.d.comb += self.out.eq(Cat(*ol))
- m.d.comb += self.intermediate_output.eq(self.i.intermediate_output)
+
+ # create outputs
+ m.d.comb += self.o.output.eq(Cat(*ol))
+ m.d.comb += self.o.intermediate_output.eq(self.i.intermediate_output)
+
return m
self.part_pts[i] = Signal(name=f"part_pts_{i}")
self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
- def eq_from(self, part_pts, inputs, part_ops):
+ def eq_from(self, part_pts, a, b, part_ops):
return [self.part_pts.eq(part_pts)] + \
[self.a.eq(a), self.b.eq(b)] + \
[self.part_ops[i].eq(part_ops[i])
return self.eq_from(rhs.part_pts, rhs.a, rhs.b, rhs.part_ops)
+class OutputData:
+
+ def __init__(self):
+ self.intermediate_output = Signal(128) # needed for unit tests
+ self.output = Signal(64)
+
+ def eq(self, rhs):
+ return [self.intermediate_output.eq(rhs.intermediate_output),
+ self.output.eq(rhs.output)]
+
+
class AllTerms(Elaboratable):
"""Set of terms to be added together
"""
pipeline registers.
:param partition_points: the input partition points.
"""
- self.i = InputData()
self.register_levels = register_levels
self.n_inputs = n_inputs
self.n_parts = n_parts
self.output_width = output_width
- self.o = AddReduceData(self.i.part_pts, n_inputs,
- output_width, n_parts)
+
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return InputData()
+
+ def ospec(self):
+ return AddReduceData(self.i.part_pts, self.n_inputs,
+ self.output_width, self.n_parts)
def elaborate(self, platform):
m = Module()
""" Intermediate output modules
"""
- def __init__(self, output_width, n_parts, partition_points):
- self.i = FinalReduceData(partition_points, output_width, n_parts)
- self.o = IntermediateData(partition_points, output_width, n_parts)
+ def __init__(self, output_width, n_parts, part_pts):
+ self.part_pts = part_pts
+ self.output_width = output_width
+ self.n_parts = n_parts
+
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return FinalReduceData(self.part_pts, self.output_width, self.n_parts)
+
+ def ospec(self):
+ return IntermediateData(self.part_pts, self.output_width, self.n_parts)
def elaborate(self, platform):
m = Module()
# parameter(s)
self.register_levels = list(register_levels)
+ self.i = self.ispec()
+ self.o = self.ospec()
+
# inputs
- self.i = InputData()
self.part_pts = self.i.part_pts
self.part_ops = self.i.part_ops
self.a = self.i.a
self.b = self.i.b
- # intermediates (needed for unit tests)
- self.intermediate_output = Signal(128)
-
# output
- self.output = Signal(64)
+ self.intermediate_output = self.o.intermediate_output
+ self.output = self.o.output
+
+ def ispec(self):
+ return InputData()
+
+ def ospec(self):
+ return OutputData()
def elaborate(self, platform):
m = Module()
part_pts = self.part_pts
n_inputs = 64 + 4
- n_parts = 8 #len(self.part_pts)
+ n_parts = 8
t = AllTerms(n_inputs, 128, n_parts, self.register_levels)
m.submodules.allterms = t
- m.d.comb += t.i.a.eq(self.a)
- m.d.comb += t.i.b.eq(self.b)
- m.d.comb += t.i.part_pts.eq(part_pts)
- for i in range(8):
- m.d.comb += t.i.part_ops[i].eq(self.part_ops[i])
+ m.d.comb += t.i.eq(self.i)
terms = t.o.terms
128,
self.register_levels,
t.o.part_pts,
- t.o.part_ops)
-
- out_part_ops = add_reduce.o.part_ops
- out_part_pts = add_reduce.o.part_pts
+ t.o.part_ops,
+ partition_step=2)
m.submodules.add_reduce = add_reduce
# final output
m.submodules.finalout = finalout = FinalOut(128, 8, part_pts)
m.d.comb += finalout.i.eq(interm.o)
- m.d.comb += self.output.eq(finalout.out)
- m.d.comb += self.intermediate_output.eq(finalout.intermediate_output)
+ m.d.comb += self.o.eq(finalout.o)
return m
projects / ieee754fpu.git / blobdiff