:param width: the bit width of the input and output
"""
- self.in0 = Signal(width)
- self.in1 = Signal(width)
- self.in2 = Signal(width)
- self.sum = Signal(width)
- self.carry = Signal(width)
+ self.in0 = Signal(width, reset_less=True)
+ self.in1 = Signal(width, reset_less=True)
+ self.in2 = Signal(width, reset_less=True)
+ self.sum = Signal(width, reset_less=True)
+ self.carry = Signal(width, reset_less=True)
def elaborate(self, platform):
"""Elaborate this module."""
:param partition_points: the input partition points
"""
self.width = width
- self.a = Signal(width)
- self.b = Signal(width)
- self.output = Signal(width)
+ self.a = Signal(width, reset_less=True)
+ self.b = Signal(width, reset_less=True)
+ self.output = Signal(width, reset_less=True)
self.partition_points = PartitionPoints(partition_points)
if not self.partition_points.fits_in_width(width):
raise ValueError("partition_points doesn't fit in width")
expanded_width += 1
expanded_width += 1
self._expanded_width = expanded_width
- # XXX these have to remain here due to some horrible nmigen
- # simulation bugs involving sync. it is *not* necessary to
- # have them here, they should (under normal circumstances)
- # be moved into elaborate, as they are entirely local
- self._expanded_a = Signal(expanded_width) # includes extra part-points
- self._expanded_b = Signal(expanded_width) # likewise.
- self._expanded_o = Signal(expanded_width) # likewise.
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
+ expanded_a = Signal(self._expanded_width, reset_less=True)
+ expanded_b = Signal(self._expanded_width, reset_less=True)
+ expanded_o = Signal(self._expanded_width, reset_less=True)
+
expanded_index = 0
# store bits in a list, use Cat later. graphviz is much cleaner
al, bl, ol, ea, eb, eo = [],[],[],[],[],[]
if i in self.partition_points:
# add extra bit set to 0 + 0 for enabled partition points
# and 1 + 0 for disabled partition points
- ea.append(self._expanded_a[expanded_index])
+ ea.append(expanded_a[expanded_index])
al.append(~self.partition_points[i]) # add extra bit in a
- eb.append(self._expanded_b[expanded_index])
+ eb.append(expanded_b[expanded_index])
bl.append(C(0)) # yes, add a zero
expanded_index += 1 # skip the extra point. NOT in the output
- ea.append(self._expanded_a[expanded_index])
- eb.append(self._expanded_b[expanded_index])
- eo.append(self._expanded_o[expanded_index])
+ ea.append(expanded_a[expanded_index])
+ eb.append(expanded_b[expanded_index])
+ eo.append(expanded_o[expanded_index])
al.append(self.a[i])
bl.append(self.b[i])
ol.append(self.output[i])
# use only one addition to take advantage of look-ahead carry and
# special hardware on FPGAs
- m.d.comb += self._expanded_o.eq(
- self._expanded_a + self._expanded_b)
+ m.d.comb += expanded_o.eq(expanded_a + expanded_b)
return m
class AddReduceData:
def __init__(self, ppoints, n_inputs, output_width, n_parts):
- self.part_ops = [Signal(2, name=f"part_ops_{i}")
+ self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
for i in range(n_parts)]
- self.inputs = [Signal(output_width, name=f"inputs[{i}]")
- for i in range(n_inputs)]
+ self.inputs = [Signal(output_width, name=f"inputs_{i}",
+ reset_less=True)
+ for i in range(n_inputs)]
self.reg_partition_points = ppoints.like()
def eq_from(self, reg_partition_points, inputs, part_ops):
class FinalReduceData:
def __init__(self, ppoints, output_width, n_parts):
- self.part_ops = [Signal(2, name=f"part_ops_{i}")
+ self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
for i in range(n_parts)]
- self.output = Signal(output_width)
+ self.output = Signal(output_width, reset_less=True)
self.reg_partition_points = ppoints.like()
def eq_from(self, reg_partition_points, output, part_ops):
m = Module()
output_width = self.output_width
- output = Signal(output_width)
+ output = Signal(output_width, reset_less=True)
if self.n_inputs == 0:
# use 0 as the default output value
m.d.comb += output.eq(0)
raise ValueError(
"not enough adder levels for specified register levels")
- # this is annoying. we have to create the modules (and terms)
- # because we need to know what they are (in order to set up the
- # interconnects back in AddReduce), but cannot do the m.d.comb +=
- # etc because this is not in elaboratable.
self.groups = AddReduceSingle.full_adder_groups(n_inputs)
- self._intermediate_terms = []
- self.adders = []
- if len(self.groups) != 0:
- self.create_next_terms()
+ n_terms = AddReduceSingle.calc_n_inputs(n_inputs, self.groups)
+ self.o = AddReduceData(partition_points, n_terms, output_width, n_parts)
- self.o = AddReduceData(partition_points, len(self._intermediate_terms),
- output_width, n_parts)
+ @staticmethod
+ def calc_n_inputs(n_inputs, groups):
+ retval = len(groups)*2
+ if n_inputs % FULL_ADDER_INPUT_COUNT == 1:
+ retval += 1
+ elif n_inputs % FULL_ADDER_INPUT_COUNT == 2:
+ retval += 2
+ else:
+ assert n_inputs % FULL_ADDER_INPUT_COUNT == 0
+ return retval
@staticmethod
def get_max_level(input_count):
input_count - FULL_ADDER_INPUT_COUNT + 1,
FULL_ADDER_INPUT_COUNT)
+ def create_next_terms(self):
+ """ create next intermediate terms, for linking up in elaborate, below
+ """
+ terms = []
+ adders = []
+
+ # create full adders for this recursive level.
+ # this shrinks N terms to 2 * (N // 3) plus the remainder
+ for i in self.groups:
+ adder_i = MaskedFullAdder(self.output_width)
+ adders.append((i, adder_i))
+ # add both the sum and the masked-carry to the next level.
+ # 3 inputs have now been reduced to 2...
+ terms.append(adder_i.sum)
+ terms.append(adder_i.mcarry)
+ # handle the remaining inputs.
+ if self.n_inputs % FULL_ADDER_INPUT_COUNT == 1:
+ terms.append(self.i.inputs[-1])
+ elif self.n_inputs % FULL_ADDER_INPUT_COUNT == 2:
+ # Just pass the terms to the next layer, since we wouldn't gain
+ # anything by using a half adder since there would still be 2 terms
+ # and just passing the terms to the next layer saves gates.
+ terms.append(self.i.inputs[-2])
+ terms.append(self.i.inputs[-1])
+ else:
+ assert self.n_inputs % FULL_ADDER_INPUT_COUNT == 0
+
+ return terms, adders
+
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
+ terms, adders = self.create_next_terms()
+
# copy the intermediate terms to the output
- for i, value in enumerate(self._intermediate_terms):
+ for i, value in enumerate(terms):
m.d.comb += self.o.inputs[i].eq(value)
# copy reg part points and part ops to output
m.d.comb += part_mask.eq(mask)
# add and link the intermediate term modules
- for i, (iidx, adder_i) in enumerate(self.adders):
+ for i, (iidx, adder_i) in enumerate(adders):
setattr(m.submodules, f"adder_{i}", adder_i)
m.d.comb += adder_i.in0.eq(self.i.inputs[iidx])
return m
- def create_next_terms(self):
-
- _intermediate_terms = []
-
- def add_intermediate_term(value):
- _intermediate_terms.append(value)
-
- # create full adders for this recursive level.
- # this shrinks N terms to 2 * (N // 3) plus the remainder
- for i in self.groups:
- adder_i = MaskedFullAdder(self.output_width)
- self.adders.append((i, adder_i))
- # add both the sum and the masked-carry to the next level.
- # 3 inputs have now been reduced to 2...
- add_intermediate_term(adder_i.sum)
- add_intermediate_term(adder_i.mcarry)
- # handle the remaining inputs.
- if self.n_inputs % FULL_ADDER_INPUT_COUNT == 1:
- add_intermediate_term(self.i.inputs[-1])
- elif self.n_inputs % FULL_ADDER_INPUT_COUNT == 2:
- # Just pass the terms to the next layer, since we wouldn't gain
- # anything by using a half adder since there would still be 2 terms
- # and just passing the terms to the next layer saves gates.
- add_intermediate_term(self.i.inputs[-2])
- add_intermediate_term(self.i.inputs[-1])
- else:
- assert self.n_inputs % FULL_ADDER_INPUT_COUNT == 0
-
- self._intermediate_terms = _intermediate_terms
-
class AddReduce(Elaboratable):
"""Recursively Add list of numbers together.
inputs = self.inputs
ilen = len(inputs)
while True:
+ groups = AddReduceSingle.full_adder_groups(len(inputs))
+ if len(groups) == 0:
+ break
next_level = AddReduceSingle(ilen, self.output_width, n_parts,
next_levels, partition_points)
mods.append(next_level)
inputs = next_level.o.inputs
ilen = len(inputs)
part_ops = next_level.i.part_ops
- groups = AddReduceSingle.full_adder_groups(len(inputs))
- if len(groups) == 0:
- break
next_level = FinalAdd(ilen, self.output_width, n_parts,
next_levels, partition_points)
# inputs
self.epps = PartitionPoints.like(epps, name="epps") # expanded points
# outputs
- self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+ self.parts = [Signal(name=f"part_{i}", reset_less=True)
+ for i in range(n_parts)]
def elaborate(self, platform):
m = Module()
self.epps = epps
# inputs
- self.a = Signal(64)
- self.b = Signal(64)
- self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
- self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.a = Signal(64, reset_less=True)
+ self.b = Signal(64, reset_less=True)
+ self.a_signed = [Signal(name=f"a_signed_{i}", reset_less=True)
+ for i in range(8)]
+ self.b_signed = [Signal(name=f"_b_signed_{i}", reset_less=True)
+ for i in range(8)]
self.pbs = Signal(pbwid, reset_less=True)
# outputs
- self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+ self.parts = [Signal(name=f"part_{i}", reset_less=True)
+ for i in range(n_parts)]
- self.not_a_term = Signal(width)
- self.neg_lsb_a_term = Signal(width)
- self.not_b_term = Signal(width)
- self.neg_lsb_b_term = Signal(width)
+ self.not_a_term = Signal(width, reset_less=True)
+ self.neg_lsb_a_term = Signal(width, reset_less=True)
+ self.not_b_term = Signal(width, reset_less=True)
+ self.neg_lsb_b_term = Signal(width, reset_less=True)
def elaborate(self, platform):
m = Module()
that some partitions requested 8-bit computation whilst others
requested 16 or 32 bit.
"""
- def __init__(self, out_wid):
- # inputs
- self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
- self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
- self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
-
- self.i8 = Signal(out_wid, reset_less=True)
- self.i16 = Signal(out_wid, reset_less=True)
- self.i32 = Signal(out_wid, reset_less=True)
- self.i64 = Signal(out_wid, reset_less=True)
-
+ def __init__(self, output_width, n_parts, partition_points):
+ self.expanded_part_points = partition_points
+ self.i = IntermediateData(partition_points, output_width, n_parts)
+ self.out_wid = output_width//2
# output
- self.out = Signal(out_wid, reset_less=True)
+ self.out = Signal(self.out_wid, reset_less=True)
+ self.intermediate_output = Signal(output_width, reset_less=True)
def elaborate(self, platform):
m = Module()
+
+ eps = self.expanded_part_points
+ m.submodules.p_8 = p_8 = Parts(8, eps, 8)
+ m.submodules.p_16 = p_16 = Parts(8, eps, 4)
+ m.submodules.p_32 = p_32 = Parts(8, eps, 2)
+ m.submodules.p_64 = p_64 = Parts(8, eps, 1)
+
+ out_part_pts = self.i.reg_partition_points
+
+ # temporaries
+ d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+
+ i8 = Signal(self.out_wid, reset_less=True)
+ i16 = Signal(self.out_wid, reset_less=True)
+ i32 = Signal(self.out_wid, reset_less=True)
+ i64 = Signal(self.out_wid, reset_less=True)
+
+ m.d.comb += p_8.epps.eq(out_part_pts)
+ m.d.comb += p_16.epps.eq(out_part_pts)
+ m.d.comb += p_32.epps.eq(out_part_pts)
+ m.d.comb += p_64.epps.eq(out_part_pts)
+
+ for i in range(len(p_8.parts)):
+ m.d.comb += d8[i].eq(p_8.parts[i])
+ for i in range(len(p_16.parts)):
+ m.d.comb += d16[i].eq(p_16.parts[i])
+ for i in range(len(p_32.parts)):
+ m.d.comb += d32[i].eq(p_32.parts[i])
+ m.d.comb += i8.eq(self.i.outputs[0])
+ m.d.comb += i16.eq(self.i.outputs[1])
+ m.d.comb += i32.eq(self.i.outputs[2])
+ m.d.comb += i64.eq(self.i.outputs[3])
+
ol = []
for i in range(8):
# select one of the outputs: d8 selects i8, d16 selects i16
# if neither d8 nor d16 are set, d32 selects either i32 or i64.
op = Signal(8, reset_less=True, name="op_%d" % i)
m.d.comb += op.eq(
- Mux(self.d8[i] | self.d16[i // 2],
- Mux(self.d8[i], self.i8.part(i * 8, 8),
- self.i16.part(i * 8, 8)),
- Mux(self.d32[i // 4], self.i32.part(i * 8, 8),
- self.i64.part(i * 8, 8))))
+ Mux(d8[i] | d16[i // 2],
+ Mux(d8[i], i8.part(i * 8, 8), i16.part(i * 8, 8)),
+ Mux(d32[i // 4], i32.part(i * 8, 8), i64.part(i * 8, 8))))
ol.append(op)
m.d.comb += self.out.eq(Cat(*ol))
+ m.d.comb += self.intermediate_output.eq(self.i.intermediate_output)
return m
return m
+class IntermediateData:
+
+ def __init__(self, ppoints, output_width, n_parts):
+ self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
+ for i in range(n_parts)]
+ self.reg_partition_points = ppoints.like()
+ self.outputs = [Signal(output_width, name="io%d" % i, reset_less=True)
+ for i in range(4)]
+ # intermediates (needed for unit tests)
+ self.intermediate_output = Signal(output_width)
+
+ def eq_from(self, reg_partition_points, outputs, intermediate_output,
+ part_ops):
+ return [self.reg_partition_points.eq(reg_partition_points)] + \
+ [self.intermediate_output.eq(intermediate_output)] + \
+ [self.outputs[i].eq(outputs[i])
+ for i in range(4)] + \
+ [self.part_ops[i].eq(part_ops[i])
+ for i in range(len(self.part_ops))]
+
+ def eq(self, rhs):
+ return self.eq_from(rhs.reg_partition_points, rhs.outputs,
+ rhs.intermediate_output, rhs.part_ops)
+
+
+class Intermediates(Elaboratable):
+ """ Intermediate output modules
+ """
+
+ def __init__(self, output_width, n_parts, partition_points):
+ self.i = FinalReduceData(partition_points, output_width, n_parts)
+ self.o = IntermediateData(partition_points, output_width, n_parts)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ out_part_ops = self.i.part_ops
+ out_part_pts = self.i.reg_partition_points
+
+ # create _output_64
+ m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
+ m.d.comb += io64.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io64.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[3].eq(io64.output)
+
+ # create _output_32
+ m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
+ m.d.comb += io32.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io32.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[2].eq(io32.output)
+
+ # create _output_16
+ m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
+ m.d.comb += io16.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io16.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[1].eq(io16.output)
+
+ # create _output_8
+ m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
+ m.d.comb += io8.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[0].eq(io8.output)
+
+ for i in range(8):
+ m.d.comb += self.o.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.reg_partition_points.eq(out_part_pts)
+ m.d.comb += self.o.intermediate_output.eq(self.i.output)
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
self.b = Signal(64)
# intermediates (needed for unit tests)
- self._intermediate_output = Signal(128)
+ self.intermediate_output = Signal(128)
# output
self.output = Signal(64)
expanded_part_pts[i * 2] = ep
m.d.comb += ep.eq(v)
+ n_inputs = 64 + 4
+ n_parts = 8 #len(self.part_pts)
+ t = AllTerms(8, n_inputs, 128, n_parts, self.register_levels,
+ eps)
+ m.submodules.allterms = t
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pbs.eq(pbs)
+ m.d.comb += t.epps.eq(eps)
+ for i in range(8):
+ m.d.comb += t.part_ops[i].eq(self.part_ops[i])
+
+ terms = t.o.inputs
+
+ add_reduce = AddReduce(terms,
+ 128,
+ self.register_levels,
+ t.o.reg_partition_points,
+ t.o.part_ops)
+
+ out_part_ops = add_reduce.o.part_ops
+ out_part_pts = add_reduce.o.reg_partition_points
+
+ m.submodules.add_reduce = add_reduce
+ m.d.comb += self.intermediate_output.eq(add_reduce.o.output)
+
+ interm = Intermediates(128, 8, expanded_part_pts)
+ m.submodules.intermediates = interm
+ m.d.comb += interm.i.eq(add_reduce.o)
+
+ # final output
+ m.submodules.finalout = finalout = FinalOut(128, 8, expanded_part_pts)
+ m.d.comb += finalout.i.eq(interm.o)
+ m.d.comb += self.output.eq(finalout.out)
+
+ return m
+
+
+class AllTerms(Elaboratable):
+ """Set of terms to be added together
+ """
+
+ def __init__(self, pbwid, n_inputs, output_width, n_parts, register_levels,
+ partition_points):
+ """Create an ``AddReduce``.
+
+ :param inputs: input ``Signal``s to be summed.
+ :param output_width: bit-width of ``output``.
+ :param register_levels: List of nesting levels that should have
+ pipeline registers.
+ :param partition_points: the input partition points.
+ """
+ self.epps = partition_points.like()
+ self.register_levels = register_levels
+ self.pbwid = pbwid
+ self.n_inputs = n_inputs
+ self.n_parts = n_parts
+ self.output_width = output_width
+ self.o = AddReduceData(self.epps, n_inputs,
+ output_width, n_parts)
+
+ self.a = Signal(64)
+ self.b = Signal(64)
+
+ self.pbs = Signal(pbwid, reset_less=True)
+ self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
+
+ def elaborate(self, platform):
+ m = Module()
+
+ pbs = self.pbs
+ eps = self.epps
+
# local variables
signs = []
for i in range(8):
m.d.comb += mod.orin[i].eq(l[i])
terms.append(mod.orout)
- add_reduce = AddReduce(terms,
- 128,
- self.register_levels,
- expanded_part_pts,
- self.part_ops)
-
- out_part_ops = add_reduce.o.part_ops
- out_part_pts = add_reduce.o.reg_partition_points
-
- m.submodules.add_reduce = add_reduce
- m.d.comb += self._intermediate_output.eq(add_reduce.o.output)
- # create _output_64
- m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
- m.d.comb += io64.intermed.eq(self._intermediate_output)
- for i in range(8):
- m.d.comb += io64.part_ops[i].eq(out_part_ops[i])
-
- # create _output_32
- m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
- m.d.comb += io32.intermed.eq(self._intermediate_output)
- for i in range(8):
- m.d.comb += io32.part_ops[i].eq(out_part_ops[i])
-
- # create _output_16
- m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
- m.d.comb += io16.intermed.eq(self._intermediate_output)
- for i in range(8):
- m.d.comb += io16.part_ops[i].eq(out_part_ops[i])
-
- # create _output_8
- m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
- m.d.comb += io8.intermed.eq(self._intermediate_output)
- for i in range(8):
- m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
-
- m.submodules.p_8 = p_8 = Parts(8, eps, len(part_8.parts))
- m.submodules.p_16 = p_16 = Parts(8, eps, len(part_16.parts))
- m.submodules.p_32 = p_32 = Parts(8, eps, len(part_32.parts))
- m.submodules.p_64 = p_64 = Parts(8, eps, len(part_64.parts))
-
- m.d.comb += p_8.epps.eq(out_part_pts)
- m.d.comb += p_16.epps.eq(out_part_pts)
- m.d.comb += p_32.epps.eq(out_part_pts)
- m.d.comb += p_64.epps.eq(out_part_pts)
+ # copy the intermediate terms to the output
+ for i, value in enumerate(terms):
+ m.d.comb += self.o.inputs[i].eq(value)
- # final output
- m.submodules.finalout = finalout = FinalOut(64)
- for i in range(len(part_8.parts)):
- m.d.comb += finalout.d8[i].eq(p_8.parts[i])
- for i in range(len(part_16.parts)):
- m.d.comb += finalout.d16[i].eq(p_16.parts[i])
- for i in range(len(part_32.parts)):
- m.d.comb += finalout.d32[i].eq(p_32.parts[i])
- m.d.comb += finalout.i8.eq(io8.output)
- m.d.comb += finalout.i16.eq(io16.output)
- m.d.comb += finalout.i32.eq(io32.output)
- m.d.comb += finalout.i64.eq(io64.output)
- m.d.comb += self.output.eq(finalout.out)
+ # copy reg part points and part ops to output
+ m.d.comb += self.o.reg_partition_points.eq(eps)
+ m.d.comb += [self.o.part_ops[i].eq(self.part_ops[i])
+ for i in range(len(self.part_ops))]
return m
m = Mul8_16_32_64()
main(m, ports=[m.a,
m.b,
- m._intermediate_output,
+ m.intermediate_output,
m.output,
*m.part_ops,
*m.part_pts.values()])
projects / ieee754fpu.git / blobdiff