skip add clock on combinatorial tests

[ieee754fpu.git] / src / ieee754 / part_mul_add / test / test_multiply.py

diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py
index 409d482f0edee991f539f5d9f18bac57ee5ad9c7..3287cbe4c6c1c304545b36f8790533b677412c78 100644 (file)
--- a/src/ieee754/part_mul_add/test/test_multiply.py
+++ b/src/ieee754/part_mul_add/test/test_multiply.py
@@ -56,10 +56,10 @@ class TestPartitionPoints(unittest.TestCase):
                 self.assertEqual((yield partition_points[1]), True)
                 self.assertEqual((yield partition_points[5]), False)
                 yield partition_point_10.eq(0)
-                yield Delay(1e-6)
+                yield Delay(0.1e-6)
                 self.assertEqual((yield mask), 0xFFFD)
                 yield partition_point_10.eq(1)
-                yield Delay(1e-6)
+                yield Delay(0.1e-6)
                 self.assertEqual((yield mask), 0xFBFD)
 
             sim.add_process(async_process)
@@ -94,7 +94,7 @@ class TestPartitionedAdder(unittest.TestCase):
                                  (0x0000, 0xFFFF)]:
                         yield module.a.eq(a)
                         yield module.b.eq(b)
-                        yield Delay(1e-6)
+                        yield Delay(0.1e-6)
                         y = 0
                         for mask in mask_list:
                             y |= mask & ((a & mask) + (b & mask))
@@ -154,7 +154,7 @@ class TestAddReduce(unittest.TestCase):
         if gen_or_check == GenOrCheck.Generate:
             for i, v in zip(inputs, values):
                 yield i.eq(v)
-        yield Delay(1e-6)
+        yield Delay(0.1e-6)
         y = 0
         for mask in mask_list:
             v = 0
@@ -235,7 +235,8 @@ class TestAddReduce(unittest.TestCase):
                     yield Tick()
             yield from generic_process(GenOrCheck.Check)
 
-        sim.add_clock(2e-6)
+        if "sync" in sim._domains:
+            sim.add_clock(2e-6)
         sim.add_process(generate_process)
         sim.add_process(check_process)
         sim.run()
@@ -459,7 +460,7 @@ class TestMul8_16_32_64(unittest.TestCase):
             yield module.a.eq(a)
             yield module.b.eq(b)
         output2, intermediate_output2 = self.simd_mul(a, b, lanes)
-        yield Delay(1e-6)
+        yield Delay(0.1e-6)
         if gen_or_check == GenOrCheck.Check:
             intermediate_output = (yield module.intermediate_output)
             self.assertEqual(intermediate_output,
@@ -632,7 +633,8 @@ class TestMul8_16_32_64(unittest.TestCase):
                         yield Tick()
                 yield from process(GenOrCheck.Check)
 
-            sim.add_clock(2e-6)
+            if "sync" in sim._domains:
+                sim.add_clock(2e-6)
             sim.add_process(generate_process)
             sim.add_process(check_process)
             sim.run()