skip add clock on combinatorial tests

[ieee754fpu.git] / src / ieee754 / part_mul_add / test / test_multiply.py

diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py
index e893ecac649b3a80dba254d99af31cb509f5e855..3287cbe4c6c1c304545b36f8790533b677412c78 100644 (file)
--- a/src/ieee754/part_mul_add/test/test_multiply.py
+++ b/src/ieee754/part_mul_add/test/test_multiply.py
@@ -14,11 +14,19 @@ import unittest
 from hashlib import sha256
 import enum
 import pdb
+from nmigen.cli import verilog, rtlil
+
+
+def create_ilang(dut, traces, test_name):
+    vl = rtlil.convert(dut, ports=traces)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
 
 
 def create_simulator(module: Any,
                      traces: List[Signal],
                      test_name: str) -> Simulator:
+    create_ilang(module, traces, test_name)
     return Simulator(module,
                      vcd_file=open(test_name + ".vcd", "w"),
                      gtkw_file=open(test_name + ".gtkw", "w"),
@@ -48,10 +56,10 @@ class TestPartitionPoints(unittest.TestCase):
                 self.assertEqual((yield partition_points[1]), True)
                 self.assertEqual((yield partition_points[5]), False)
                 yield partition_point_10.eq(0)
-                yield Delay(1e-6)
+                yield Delay(0.1e-6)
                 self.assertEqual((yield mask), 0xFFFD)
                 yield partition_point_10.eq(1)
-                yield Delay(1e-6)
+                yield Delay(0.1e-6)
                 self.assertEqual((yield mask), 0xFBFD)
 
             sim.add_process(async_process)
@@ -86,7 +94,7 @@ class TestPartitionedAdder(unittest.TestCase):
                                  (0x0000, 0xFFFF)]:
                         yield module.a.eq(a)
                         yield module.b.eq(b)
-                        yield Delay(1e-6)
+                        yield Delay(0.1e-6)
                         y = 0
                         for mask in mask_list:
                             y |= mask & ((a & mask) + (b & mask))
@@ -146,7 +154,7 @@ class TestAddReduce(unittest.TestCase):
         if gen_or_check == GenOrCheck.Generate:
             for i, v in zip(inputs, values):
                 yield i.eq(v)
-        yield Delay(1e-6)
+        yield Delay(0.1e-6)
         y = 0
         for mask in mask_list:
             v = 0
@@ -227,7 +235,8 @@ class TestAddReduce(unittest.TestCase):
                     yield Tick()
             yield from generic_process(GenOrCheck.Check)
 
-        sim.add_clock(2e-6)
+        if "sync" in sim._domains:
+            sim.add_clock(2e-6)
         sim.add_process(generate_process)
         sim.add_process(check_process)
         sim.run()
@@ -256,12 +265,9 @@ class TestAddReduce(unittest.TestCase):
         if len(register_levels) != 0:
             file_name += f"-{'_'.join(map(repr, register_levels))}"
         file_name += f"-{input_count:02d}"
-        with create_simulator(module,
-                              [partition_4,
-                               partition_8,
-                               *inputs,
-                               module.o.output],
-                              file_name) as sim:
+        ports = [partition_4, partition_8, *inputs, module.o.output]
+        #create_ilang(module, ports, file_name)
+        with create_simulator(module, ports, file_name) as sim:
             self.subtest_run_sim(input_count,
                                  sim,
                                  partition_4,
@@ -454,9 +460,9 @@ class TestMul8_16_32_64(unittest.TestCase):
             yield module.a.eq(a)
             yield module.b.eq(b)
         output2, intermediate_output2 = self.simd_mul(a, b, lanes)
-        yield Delay(1e-6)
+        yield Delay(0.1e-6)
         if gen_or_check == GenOrCheck.Check:
-            intermediate_output = (yield module._intermediate_output)
+            intermediate_output = (yield module.intermediate_output)
             self.assertEqual(intermediate_output,
                              intermediate_output2,
                              f"0x{intermediate_output:X} "
@@ -522,7 +528,7 @@ class TestMul8_16_32_64(unittest.TestCase):
             file_name += f"-{'_'.join(map(repr, register_levels))}"
         ports = [module.a,
                  module.b,
-                 module._intermediate_output,
+                 module.intermediate_output,
                  module.output]
         ports.extend(module.part_ops)
         ports.extend(module.part_pts.values())
@@ -627,7 +633,8 @@ class TestMul8_16_32_64(unittest.TestCase):
                         yield Tick()
                 yield from process(GenOrCheck.Check)
 
-            sim.add_clock(2e-6)
+            if "sync" in sim._domains:
+                sim.add_clock(2e-6)
             sim.add_process(generate_process)
             sim.add_process(check_process)
             sim.run()