from nmigen.cli import verilog, rtlil
from nmigen.lib.coding import PriorityEncoder
from nmigen.hdl.rec import Record, Layout
-from stageapi import _spec
+from nmutil.stageapi import _spec
from collections.abc import Sequence
-from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage
+from .nmoperator import eq
+from .iocontrol import NextControl, PrevControl
class MultiInControlBase(Elaboratable):
self.stage.setup(m, r_data)
# multiplexer id taken from n_mux
- mid = self.n_mux.m_id
+ muxid = self.n_mux.m_id
+ print ("self.n_mux", self.n_mux)
+ print ("self.n_mux.m_id", self.n_mux.m_id)
# temporaries
p_valid_i = Signal(reset_less=True)
# the only output "active" is then selected by the muxid
for i in range(len(self.n)):
m.d.comb += self.n[i].valid_o.eq(0)
- data_valid = self.n[mid].valid_o
- m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].ready_i)
+ data_valid = self.n[muxid].valid_o
+ m.d.comb += self.p.ready_o.eq(~data_valid | self.n[muxid].ready_i)
m.d.comb += data_valid.eq(p_valid_i | \
- (~self.n[mid].ready_i & data_valid))
+ (~self.n[muxid].ready_i & data_valid))
with m.If(pv):
m.d.comb += eq(r_data, self.p.data_i)
- m.d.comb += eq(self.n[mid].data_o, self.process(r_data))
+ m.d.comb += eq(self.n[muxid].data_o, self.process(r_data))
return m
# HACK: stage is also the n-way multiplexer
CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
- # HACK: n-mux is also the stage... so set the muxid equal to input mid
- stage.m_id = self.p.data_i.mid
+ # HACK: n-mux is also the stage... so set the muxid equal to input muxid
+ print ("combmuxout", self.p.data_i.muxid)
+ stage.m_id = self.p.data_i.muxid
if __name__ == '__main__':
+ from nmutil.test.example_buf_pipe import ExampleStage
dut = PriorityCombMuxInPipe(ExampleStage)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_combpipe.il", "w") as f: