add bug #148 record

[ieee754fpu.git] / src / nmutil / singlepipe.py

diff --git a/src/nmutil/singlepipe.py b/src/nmutil/singlepipe.py
index a526be7be4258df041ff7f3fa9e2caa34b06ca19..4880a819f22caf361a276083a40e618a9b538383 100644 (file)
--- a/src/nmutil/singlepipe.py
+++ b/src/nmutil/singlepipe.py
@@ -1,6 +1,7 @@
 """ Pipeline API.  For multi-input and multi-output variants, see multipipe.
 
     Associated development bugs:
+    * http://bugs.libre-riscv.org/show_bug.cgi?id=148
     * http://bugs.libre-riscv.org/show_bug.cgi?id=64
     * http://bugs.libre-riscv.org/show_bug.cgi?id=57
 
@@ -13,7 +14,7 @@
     PipelineAPI:
 
         * StageAPI: combinatorial (NO REGISTERS / LATCHES PERMITTED)
-        * PipelineAPI: synchronous (registers / latches MAY added on demand)
+        * PipelineAPI: synchronous registers / latches get added here
 
     RecordBasedStage:
     ----------------
@@ -951,14 +952,14 @@ class FIFOControl(ControlBase):
         m.submodules.fn = fn = NextControl()
         fn.valid_o, fn.ready_i, fn.data_o  = fifo.readable, fifo.re, fifo.dout
         connections = fn._connect_out(self.n, fn=nmoperator.cat)
+        valid_eq, ready_eq, data_o = connections
 
         # ok ok so we can't just do the ready/valid eqs straight:
         # first 2 from connections are the ready/valid, 3rd is data.
         if self.fwft:
-            m.d.comb += connections[:2] # combinatorial on next ready/valid
+            m.d.comb += [valid_eq, ready_eq] # combinatorial on next ready/valid
         else:
-            m.d.sync += connections[:2]  # non-fwft mode needs sync
-        data_o = connections[2] # get the data
+            m.d.sync += [valid_eq, ready_eq] # non-fwft mode needs sync
         data_o = self._postprocess(data_o) # XXX TBD, does nothing right now
         m.d.comb += data_o