add ignore on *.v and *.il

diff --git a/.gitignore b/.gitignore
index 2fc73bb442ed18a7c02d4d59d3ab12671728611e..e77dcf4f47f850ae62256eb18b8b93415b52ac38 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,5 @@
 *.py?
 .*.sw?
 __pycache__
+*.v
+*.il

diff --git a/src/ieee754/add/nmigen_add_experiment.py b/src/ieee754/add/nmigen_add_experiment.py
deleted file mode 100644 (file)
index 773e3ae..0000000
--- a/src/ieee754/add/nmigen_add_experiment.py
+++ /dev/null
@@ -1,28 +0,0 @@
-# IEEE Floating Point Adder (Single Precision)
-# Copyright (C) Jonathan P Dawson 2013
-# 2013-12-12
-
-from nmigen.cli import main, verilog
-from ieee754.fpadd.statemachine import FPADDBase, FPADD
-from ieee754.fpadd.pipeline import FPADDMuxInOut
-
-if __name__ == "__main__":
-    if True:
-        alu = FPADD(width=32, id_wid=5, single_cycle=True)
-        main(alu, ports=alu.rs[0][0].ports() + \
-                        alu.rs[0][1].ports() + \
-                        alu.res[0].ports() + \
-                        [alu.ids.in_mid, alu.ids.out_mid])
-    else:
-        alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
-        main(alu, ports=[alu.in_a, alu.in_b] + \
-                        alu.in_t.ports() + \
-                        alu.out_z.ports() + \
-                        [alu.in_mid, alu.out_mid])
-
-
-    # works... but don't use, just do "python fname.py convert -t v"
-    #print (verilog.convert(alu, ports=[
-    #                        ports=alu.in_a.ports() + \
-    #                              alu.in_b.ports() + \
-    #                              alu.out_z.ports())

diff --git a/src/ieee754/add/test_add.py b/src/ieee754/add/test_add.py
deleted file mode 100644 (file)
index 989cf48..0000000
--- a/src/ieee754/add/test_add.py
+++ /dev/null
@@ -1,78 +0,0 @@
-from operator import add
-
-from nmigen import Module, Signal
-from nmigen.compat.sim import run_simulation
-
-from nmigen_add_experiment import FPADD
-
-from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
-                                is_inf, is_pos_inf, is_neg_inf,
-                                match, get_rs_case, check_rs_case, run_test,
-                                run_edge_cases, run_corner_cases)
-
-def testbench(dut):
-    yield from check_rs_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
-    yield from check_rs_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
-    yield from check_rs_case(dut, 0x00000047, 0x80000048, 0x80000001)
-    yield from check_rs_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
-    yield from check_rs_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
-    yield from check_rs_case(dut, 0, 0, 0)
-    yield from check_rs_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
-    yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    #yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    yield from check_rs_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
-    yield from check_rs_case(dut, 0x42540000, 0xC2540000, 0x00000000)
-    yield from check_rs_case(dut, 0xC2540000, 0x42540000, 0x00000000)
-    yield from check_rs_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
-    yield from check_rs_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
-    yield from check_rs_case(dut, 0x40000000, 0xc0000000, 0x00000000)
-    yield from check_rs_case(dut, 0x3F800000, 0x40000000, 0x40400000)
-    yield from check_rs_case(dut, 0x40000000, 0x3F800000, 0x40400000)
-    yield from check_rs_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
-    yield from check_rs_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
-    yield from check_rs_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
-    yield from check_rs_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
-    yield from check_rs_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
-    yield from check_rs_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
-    yield from check_rs_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
-    yield from check_rs_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
-    yield from check_rs_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
-    yield from check_rs_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
-    yield from check_rs_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
-    yield from check_rs_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
-    yield from check_rs_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
-    yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    yield from check_rs_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
-    yield from check_rs_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
-    yield from check_rs_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
-    yield from check_rs_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
-    yield from check_rs_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
-    yield from check_rs_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
-    yield from check_rs_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
-    yield from check_rs_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
-    yield from check_rs_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
-    yield from check_rs_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
-    yield from check_rs_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
-    #yield from check_rs_case(dut, 1, 0, 1)
-    #yield from check_rs_case(dut, 1, 1, 1)
-
-    count = 0
-
-    #regression tests
-    stimulus_a = [0x80000000, 0x22cb525a, 0x40000000, 0x83e73d5c,
-                  0xbf9b1e94, 0x34082401,
-                    0x5e8ef81, 0x5c75da81, 0x2b017]
-    stimulus_b = [0xff800001, 0xadd79efa, 0xC0000000, 0x1c800000,
-                  0xc038ed3a, 0xb328cd45, 
-                    0x114f3db, 0x2f642a39, 0xff3807ab]
-    yield from run_test(dut, stimulus_a, stimulus_b, add, get_rs_case)
-    count += len(stimulus_a)
-    print (count, "vectors passed")
-
-    yield from run_corner_cases(dut, count, add, get_rs_case)
-    yield from run_edge_cases(dut, count, add, get_rs_case)
-
-if __name__ == '__main__':
-    dut = FPADD(width=32, id_wid=5, single_cycle=True)
-    run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
-

diff --git a/src/ieee754/add/test_add16.py b/src/ieee754/add/test_add16.py
deleted file mode 100644 (file)
index f39ae8a..0000000
--- a/src/ieee754/add/test_add16.py
+++ /dev/null
@@ -1,44 +0,0 @@
-from operator import add
-
-from nmigen import Module, Signal
-from nmigen.compat.sim import run_simulation
-
-from nmigen_add_experiment import FPADD
-
-from unit_test_half import (get_mantissa, get_exponent, get_sign, is_nan,
-                                is_inf, is_pos_inf, is_neg_inf,
-                                match, get_case, check_case, run_test,
-                                run_edge_cases, run_corner_cases)
-
-def testbench(dut):
-    #yield from check_case(dut, 0x7800, 0xff6f, 0xff6f)
-    #yield from check_case(dut, 0x0000, 0x7c32, 0x7e32)
-    #yield from check_case(dut, 0x0000, 0x7da9, 0x7fa9)
-    #yield from check_case(dut, 0x0000, 0x7ea0, 0x7ea0)
-    #yield from check_case(dut, 0x7c9a, 0x8000, 0x7e9a)
-    #yield from check_case(dut, 0x7d5e, 0x0000, 0x7f5e)
-    #yield from check_case(dut, 0x8000, 0x7c8c, 0x7e8c)
-    #yield from check_case(dut, 0x8000, 0xfc55, 0xfe55)
-    #yield from check_case(dut, 0x8000, 0x7e1a, 0x7e1a)
-
-    #yield from check_case(dut, 0x8000, 0xfc01, 0x7e00)
-    yield from check_case(dut, 0xfc00, 0x7c00, 0x7e00)
-    yield from check_case(dut, 0x8000, 0, 0)
-    yield from check_case(dut, 0, 0, 0)
-
-    count = 0
-
-    #regression tests
-    stimulus_a = [ 0x8000, 0x8000 ]
-    stimulus_b = [ 0x0000, 0xfc01 ]
-    yield from run_test(dut, stimulus_a, stimulus_b, add)
-    count += len(stimulus_a)
-    print (count, "vectors passed")
-
-    yield from run_corner_cases(dut, count, add)
-    yield from run_edge_cases(dut, count, add)
-
-if __name__ == '__main__':
-    dut = FPADD(width=16, single_cycle=True)
-    run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")
-

diff --git a/src/ieee754/add/test_add64.py b/src/ieee754/add/test_add64.py
deleted file mode 100644 (file)
index dcca12c..0000000
--- a/src/ieee754/add/test_add64.py
+++ /dev/null
@@ -1,45 +0,0 @@
-from nmigen import Module, Signal
-from nmigen.compat.sim import run_simulation
-from operator import add
-
-from nmigen_add_experiment import FPADD
-
-import sys
-import atexit
-from random import randint
-from random import seed
-
-from unit_test_double import (get_mantissa, get_exponent, get_sign, is_nan,
-                                is_inf, is_pos_inf, is_neg_inf,
-                                match, get_case, check_case, run_test,
-                                run_edge_cases, run_corner_cases)
-
-
-def testbench(dut):
-    yield from check_case(dut, 0, 0, 0)
-    yield from check_case(dut, 0x3FF0000000000000, 0x4000000000000000,
-                               0x4008000000000000)
-    yield from check_case(dut, 0x4000000000000000, 0x3FF0000000000000,
-                               0x4008000000000000)
-    yield from check_case(dut, 0x4056C00000000000, 0x4042800000000000,
-                               0x4060000000000000)
-    yield from check_case(dut, 0x4056C00000000000, 0x4042EA3D70A3D70A,
-                               0x40601A8F5C28F5C2)
-
-    count = 0
-
-    #regression tests
-    stimulus_a = [0x3ff00000000000c5, 0xff80000000000000]
-    stimulus_b = [0xbd28a404211fb72b, 0x7f80000000000000]
-    yield from run_test(dut, stimulus_a, stimulus_b, add)
-    count += len(stimulus_a)
-    print (count, "vectors passed")
-
-    yield from run_corner_cases(dut, count, add)
-    yield from run_edge_cases(dut, count, add)
-
-
-if __name__ == '__main__':
-    dut = FPADD(width=64, single_cycle=False)
-    run_simulation(dut, testbench(dut), vcd_name="test_add64.vcd")
-

diff --git a/src/ieee754/add/test_add_base.py b/src/ieee754/add/test_add_base.py
deleted file mode 100644 (file)
index 248f719..0000000
--- a/src/ieee754/add/test_add_base.py
+++ /dev/null
@@ -1,94 +0,0 @@
-from random import randint
-from operator import add
-
-from nmigen import Module, Signal
-from nmigen.compat.sim import run_simulation
-
-from nmigen_add_experiment import FPADDBase, FPADDBaseMod
-
-def get_case(dut, a, b, mid):
-    yield dut.in_mid.eq(mid)
-    yield dut.in_a.eq(a)
-    yield dut.in_b.eq(b)
-    yield dut.in_t.stb.eq(1)
-    yield
-    yield
-    yield
-    yield
-    ack = (yield dut.in_t.ack)
-    assert ack == 0
-
-    yield dut.in_t.stb.eq(0)
-
-    yield dut.out_z.ack.eq(1)
-
-    while True:
-        out_z_stb = (yield dut.out_z.stb)
-        if not out_z_stb:
-            yield
-            continue
-        out_z = yield dut.out_z.v
-        out_mid = yield dut.out_mid
-        yield dut.out_z.ack.eq(0)
-        yield
-        break
-
-    return out_z, out_mid
-
-def check_case(dut, a, b, z, mid=None):
-    if mid is None:
-        mid = randint(0, 6)
-    out_z, out_mid = yield from get_case(dut, a, b, mid)
-    assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
-    assert out_mid == mid, "Output mid 0x%x != expected 0x%x" % (out_mid, mid)
-
-
-
-def testbench(dut):
-    yield from check_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
-    yield from check_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
-    yield from check_case(dut, 0x00000047, 0x80000048, 0x80000001)
-    yield from check_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
-    yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
-    yield from check_case(dut, 0, 0, 0)
-    yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
-    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    yield from check_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
-    yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000)
-    yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000)
-    yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
-    yield from check_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
-    yield from check_case(dut, 0x40000000, 0xc0000000, 0x00000000)
-    yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
-    yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
-    yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
-    yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
-    yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
-    yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
-    yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
-    yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
-    yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
-    yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
-    yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
-    yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
-    yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
-    yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
-    yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
-    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
-    yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
-    yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
-    yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
-    yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
-    yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
-    yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
-    yield from check_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
-    yield from check_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
-    yield from check_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
-    yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
-
-if __name__ == '__main__':
-    dut = FPADDBaseMod(width=32, id_wid=5, single_cycle=True)
-    run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
-

diff --git a/src/ieee754/fpadd/nmigen_add_experiment.py b/src/ieee754/fpadd/nmigen_add_experiment.py
new file mode 100644 (file)
index 0000000..773e3ae
--- /dev/null
+++ b/src/ieee754/fpadd/nmigen_add_experiment.py
@@ -0,0 +1,28 @@
+# IEEE Floating Point Adder (Single Precision)
+# Copyright (C) Jonathan P Dawson 2013
+# 2013-12-12
+
+from nmigen.cli import main, verilog
+from ieee754.fpadd.statemachine import FPADDBase, FPADD
+from ieee754.fpadd.pipeline import FPADDMuxInOut
+
+if __name__ == "__main__":
+    if True:
+        alu = FPADD(width=32, id_wid=5, single_cycle=True)
+        main(alu, ports=alu.rs[0][0].ports() + \
+                        alu.rs[0][1].ports() + \
+                        alu.res[0].ports() + \
+                        [alu.ids.in_mid, alu.ids.out_mid])
+    else:
+        alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
+        main(alu, ports=[alu.in_a, alu.in_b] + \
+                        alu.in_t.ports() + \
+                        alu.out_z.ports() + \
+                        [alu.in_mid, alu.out_mid])
+
+
+    # works... but don't use, just do "python fname.py convert -t v"
+    #print (verilog.convert(alu, ports=[
+    #                        ports=alu.in_a.ports() + \
+    #                              alu.in_b.ports() + \
+    #                              alu.out_z.ports())

diff --git a/src/ieee754/fpadd/test/test_add.py b/src/ieee754/fpadd/test/test_add.py
new file mode 100644 (file)
index 0000000..989cf48
--- /dev/null
+++ b/src/ieee754/fpadd/test/test_add.py
@@ -0,0 +1,78 @@
+from operator import add
+
+from nmigen import Module, Signal
+from nmigen.compat.sim import run_simulation
+
+from nmigen_add_experiment import FPADD
+
+from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
+                                is_inf, is_pos_inf, is_neg_inf,
+                                match, get_rs_case, check_rs_case, run_test,
+                                run_edge_cases, run_corner_cases)
+
+def testbench(dut):
+    yield from check_rs_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
+    yield from check_rs_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
+    yield from check_rs_case(dut, 0x00000047, 0x80000048, 0x80000001)
+    yield from check_rs_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
+    yield from check_rs_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
+    yield from check_rs_case(dut, 0, 0, 0)
+    yield from check_rs_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
+    yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    #yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    yield from check_rs_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
+    yield from check_rs_case(dut, 0x42540000, 0xC2540000, 0x00000000)
+    yield from check_rs_case(dut, 0xC2540000, 0x42540000, 0x00000000)
+    yield from check_rs_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
+    yield from check_rs_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
+    yield from check_rs_case(dut, 0x40000000, 0xc0000000, 0x00000000)
+    yield from check_rs_case(dut, 0x3F800000, 0x40000000, 0x40400000)
+    yield from check_rs_case(dut, 0x40000000, 0x3F800000, 0x40400000)
+    yield from check_rs_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
+    yield from check_rs_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
+    yield from check_rs_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
+    yield from check_rs_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
+    yield from check_rs_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
+    yield from check_rs_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
+    yield from check_rs_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
+    yield from check_rs_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
+    yield from check_rs_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
+    yield from check_rs_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
+    yield from check_rs_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
+    yield from check_rs_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
+    yield from check_rs_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
+    yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    yield from check_rs_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
+    yield from check_rs_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
+    yield from check_rs_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
+    yield from check_rs_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
+    yield from check_rs_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
+    yield from check_rs_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
+    yield from check_rs_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
+    yield from check_rs_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
+    yield from check_rs_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
+    yield from check_rs_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
+    yield from check_rs_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
+    #yield from check_rs_case(dut, 1, 0, 1)
+    #yield from check_rs_case(dut, 1, 1, 1)
+
+    count = 0
+
+    #regression tests
+    stimulus_a = [0x80000000, 0x22cb525a, 0x40000000, 0x83e73d5c,
+                  0xbf9b1e94, 0x34082401,
+                    0x5e8ef81, 0x5c75da81, 0x2b017]
+    stimulus_b = [0xff800001, 0xadd79efa, 0xC0000000, 0x1c800000,
+                  0xc038ed3a, 0xb328cd45, 
+                    0x114f3db, 0x2f642a39, 0xff3807ab]
+    yield from run_test(dut, stimulus_a, stimulus_b, add, get_rs_case)
+    count += len(stimulus_a)
+    print (count, "vectors passed")
+
+    yield from run_corner_cases(dut, count, add, get_rs_case)
+    yield from run_edge_cases(dut, count, add, get_rs_case)
+
+if __name__ == '__main__':
+    dut = FPADD(width=32, id_wid=5, single_cycle=True)
+    run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
+

diff --git a/src/ieee754/fpadd/test/test_add16.py b/src/ieee754/fpadd/test/test_add16.py
new file mode 100644 (file)
index 0000000..f39ae8a
--- /dev/null
+++ b/src/ieee754/fpadd/test/test_add16.py
@@ -0,0 +1,44 @@
+from operator import add
+
+from nmigen import Module, Signal
+from nmigen.compat.sim import run_simulation
+
+from nmigen_add_experiment import FPADD
+
+from unit_test_half import (get_mantissa, get_exponent, get_sign, is_nan,
+                                is_inf, is_pos_inf, is_neg_inf,
+                                match, get_case, check_case, run_test,
+                                run_edge_cases, run_corner_cases)
+
+def testbench(dut):
+    #yield from check_case(dut, 0x7800, 0xff6f, 0xff6f)
+    #yield from check_case(dut, 0x0000, 0x7c32, 0x7e32)
+    #yield from check_case(dut, 0x0000, 0x7da9, 0x7fa9)
+    #yield from check_case(dut, 0x0000, 0x7ea0, 0x7ea0)
+    #yield from check_case(dut, 0x7c9a, 0x8000, 0x7e9a)
+    #yield from check_case(dut, 0x7d5e, 0x0000, 0x7f5e)
+    #yield from check_case(dut, 0x8000, 0x7c8c, 0x7e8c)
+    #yield from check_case(dut, 0x8000, 0xfc55, 0xfe55)
+    #yield from check_case(dut, 0x8000, 0x7e1a, 0x7e1a)
+
+    #yield from check_case(dut, 0x8000, 0xfc01, 0x7e00)
+    yield from check_case(dut, 0xfc00, 0x7c00, 0x7e00)
+    yield from check_case(dut, 0x8000, 0, 0)
+    yield from check_case(dut, 0, 0, 0)
+
+    count = 0
+
+    #regression tests
+    stimulus_a = [ 0x8000, 0x8000 ]
+    stimulus_b = [ 0x0000, 0xfc01 ]
+    yield from run_test(dut, stimulus_a, stimulus_b, add)
+    count += len(stimulus_a)
+    print (count, "vectors passed")
+
+    yield from run_corner_cases(dut, count, add)
+    yield from run_edge_cases(dut, count, add)
+
+if __name__ == '__main__':
+    dut = FPADD(width=16, single_cycle=True)
+    run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")
+

diff --git a/src/ieee754/fpadd/test/test_add64.py b/src/ieee754/fpadd/test/test_add64.py
new file mode 100644 (file)
index 0000000..dcca12c
--- /dev/null
+++ b/src/ieee754/fpadd/test/test_add64.py
@@ -0,0 +1,45 @@
+from nmigen import Module, Signal
+from nmigen.compat.sim import run_simulation
+from operator import add
+
+from nmigen_add_experiment import FPADD
+
+import sys
+import atexit
+from random import randint
+from random import seed
+
+from unit_test_double import (get_mantissa, get_exponent, get_sign, is_nan,
+                                is_inf, is_pos_inf, is_neg_inf,
+                                match, get_case, check_case, run_test,
+                                run_edge_cases, run_corner_cases)
+
+
+def testbench(dut):
+    yield from check_case(dut, 0, 0, 0)
+    yield from check_case(dut, 0x3FF0000000000000, 0x4000000000000000,
+                               0x4008000000000000)
+    yield from check_case(dut, 0x4000000000000000, 0x3FF0000000000000,
+                               0x4008000000000000)
+    yield from check_case(dut, 0x4056C00000000000, 0x4042800000000000,
+                               0x4060000000000000)
+    yield from check_case(dut, 0x4056C00000000000, 0x4042EA3D70A3D70A,
+                               0x40601A8F5C28F5C2)
+
+    count = 0
+
+    #regression tests
+    stimulus_a = [0x3ff00000000000c5, 0xff80000000000000]
+    stimulus_b = [0xbd28a404211fb72b, 0x7f80000000000000]
+    yield from run_test(dut, stimulus_a, stimulus_b, add)
+    count += len(stimulus_a)
+    print (count, "vectors passed")
+
+    yield from run_corner_cases(dut, count, add)
+    yield from run_edge_cases(dut, count, add)
+
+
+if __name__ == '__main__':
+    dut = FPADD(width=64, single_cycle=False)
+    run_simulation(dut, testbench(dut), vcd_name="test_add64.vcd")
+

diff --git a/src/ieee754/fpadd/test/test_add_base.py b/src/ieee754/fpadd/test/test_add_base.py
new file mode 100644 (file)
index 0000000..248f719
--- /dev/null
+++ b/src/ieee754/fpadd/test/test_add_base.py
@@ -0,0 +1,94 @@
+from random import randint
+from operator import add
+
+from nmigen import Module, Signal
+from nmigen.compat.sim import run_simulation
+
+from nmigen_add_experiment import FPADDBase, FPADDBaseMod
+
+def get_case(dut, a, b, mid):
+    yield dut.in_mid.eq(mid)
+    yield dut.in_a.eq(a)
+    yield dut.in_b.eq(b)
+    yield dut.in_t.stb.eq(1)
+    yield
+    yield
+    yield
+    yield
+    ack = (yield dut.in_t.ack)
+    assert ack == 0
+
+    yield dut.in_t.stb.eq(0)
+
+    yield dut.out_z.ack.eq(1)
+
+    while True:
+        out_z_stb = (yield dut.out_z.stb)
+        if not out_z_stb:
+            yield
+            continue
+        out_z = yield dut.out_z.v
+        out_mid = yield dut.out_mid
+        yield dut.out_z.ack.eq(0)
+        yield
+        break
+
+    return out_z, out_mid
+
+def check_case(dut, a, b, z, mid=None):
+    if mid is None:
+        mid = randint(0, 6)
+    out_z, out_mid = yield from get_case(dut, a, b, mid)
+    assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
+    assert out_mid == mid, "Output mid 0x%x != expected 0x%x" % (out_mid, mid)
+
+
+
+def testbench(dut):
+    yield from check_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
+    yield from check_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
+    yield from check_case(dut, 0x00000047, 0x80000048, 0x80000001)
+    yield from check_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
+    yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
+    yield from check_case(dut, 0, 0, 0)
+    yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
+    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    yield from check_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
+    yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000)
+    yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000)
+    yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
+    yield from check_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
+    yield from check_case(dut, 0x40000000, 0xc0000000, 0x00000000)
+    yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
+    yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
+    yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
+    yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
+    yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
+    yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
+    yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
+    yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
+    yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
+    yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
+    yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
+    yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
+    yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
+    yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
+    yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
+    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
+    yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
+    yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
+    yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
+    yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
+    yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
+    yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
+    yield from check_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
+    yield from check_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
+    yield from check_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
+    yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
+
+if __name__ == '__main__':
+    dut = FPADDBaseMod(width=32, id_wid=5, single_cycle=True)
+    run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
+