- # resize inputs to correct bit-width and optionally add in
- # pipeline registers
- resized_input_assignments = [self._resized_inputs[i].eq(self.inputs[i])
- for i in range(len(self.inputs))]
- copy_part_ops = [self.out_part_ops[i].eq(self.part_ops[i])
- for i in range(len(self.part_ops))]
- if 0 in self.register_levels:
- m.d.sync += copy_part_ops
- m.d.sync += resized_input_assignments
- m.d.sync += self._reg_partition_points.eq(self.partition_points)
- else:
- m.d.comb += copy_part_ops
- m.d.comb += resized_input_assignments
- m.d.comb += self._reg_partition_points.eq(self.partition_points)
-