fix mismatched comb process delays

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index 073396cd9e1dc2fb6ed6d23a20a21247dfab0a03..d7aeded694f783ccb2b2982fe25172918af5a427 100755 (executable)
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -275,6 +275,8 @@ class TestDivPipeCore(unittest.TestCase):
                            gtkw_file=open(f"{base_name}.gtkw", "w"),
                            traces=[*dut.traces()]):
             def generate_process():
+                if not sync:
+                    yield Delay(1e-6)
                 for test_case in test_cases:
                     if sync:
                         yield Tick()
@@ -313,7 +315,7 @@ class TestDivPipeCore(unittest.TestCase):
                                          str(test_case))
             if sync:
                 sim.add_clock(2e-6)
-            silent = False
+            silent = True
             sim.add_process(trace_process(generate_process, "generate:", silent=silent))
             sim.add_process(trace_process(check_process, "check:", silent=silent))
             sim.run()