random modifications got semi-correct output
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 22 Jul 2019 15:55:04 +0000 (16:55 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 22 Jul 2019 15:55:04 +0000 (16:55 +0100)
src/ieee754/fpcommon/test/fpmux.py
src/ieee754/fpdiv/div0.py
src/ieee754/fpdiv/div2.py
src/ieee754/fpdiv/pipeline.py

index 92d18e979d6e3aa1d49a660d0d0f1ab11dab0af1..5228ed6b158fe10779c89dc669674c57b0c9615f 100644 (file)
@@ -168,8 +168,8 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 op1 = randint(0, (1<<width)-1)
                 op2 = randint(0, (1<<width)-1)
 
-                op2 = 0x4000
-                op1 = 0x4300
+                op2 = 0x4100
+                op1 = 0x4000
                 #op2 = 0x3c00
                 vals.append((op1, op2,))
     return vals
index 763d0be6ea92f30bdad48dae91a73f5b1ff856b8..7b1d24f473aa09fe842205feac9ef5296051c078 100644 (file)
@@ -73,7 +73,7 @@ class FPDivStage0Mod(Elaboratable):
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.dividend[-len(am0):].eq(am0), # TODO: check
+                         self.o.dividend[len(self.i.a.m):].eq(am0), # TODO: check
                          self.o.divisor_radicand.eq(bm0), # TODO: check
                          self.o.operation.eq(Const(0)) # TODO check: DIV
                 ]
index 8fb5b8c27f0aa1e9ff4e25bf1dee4e352a7176a9..83b1e4f4aee7bf639bb292b83a00fda6812198b5 100644 (file)
@@ -35,8 +35,6 @@ class FPDivStage2Mod(FPState, Elaboratable):
         """ links module to inputs and outputs
         """
         m.submodules.div1 = self
-        #m.submodules.div1_out_overflow = self.o.of
-
         m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
index c6d6ca10a76cd8d0e1aee11e469e1fbf3e49c563..b265bd18e4166612c3a01331a2c7f710673ea0a8 100644 (file)
@@ -164,7 +164,7 @@ class FPDIVMuxInOut(ReservationStations):
         # also: round up to nearest radix
         fmt.m_width = roundup(fmt.m_width + 4, log2_radix)
 
-        cfg = DivPipeCoreConfig(fmt.m_width, 0*fmt.fraction_width, log2_radix)
+        cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
 
         self.pspec.fpformat = fmt
         self.pspec.log2_radix = log2_radix