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diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 2c6ec33a3012874063bb6ccd36d84dd1f02f2d4a..6cb8711557ef248e74ebde6e3a4d5f9916afe369 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -71,7 +71,7 @@ class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreInputData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
@@ -91,7 +91,7 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
         """ Assign member signals. """
         print (self, rhs)
         return DivPipeCoreInterstageData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
@@ -110,7 +110,7 @@ class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreOutputData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeBaseStage: