README.md

   1 # A framework for building SoCs with nMigen
   2
   3 **LambdaSoC is a work in progress. Please keep in mind that some interfaces will undergo breaking changes as they evolve and/or get moved [upstream][nmigen-soc].**
   4
   5 ## Installation
   6
   7 ```
   8 git clone https://github.com/lambdaconcept/lambdasoc
   9 cd lambdasoc
  10 git submodule update --init --recursive
  11
  12 pip install -r requirements.txt
  13 python setup.py install
  14 ```
  15
  16 ## Quick start
  17
  18 Let's build and run the SoC example at [examples/sram_soc.py][sram_soc]. It is composed of a [Minerva][minerva] CPU, SRAM storage, an UART and a timer.
  19
  20 ##### Requirements
  21 * A `riscv64-unknown-elf` GNU toolchain, to build the first-stage bootloader
  22 * A [supported platform][nmigen-boards] with enough resources to fit the SoC
  23
  24 Here, we build the SoC for the `nmigen_boards.arty_a7.ArtyA7Platform`:
  25 ```
  26 python examples/sram_soc.py --baudrate=9600 nmigen_boards.arty_a7.ArtyA7Platform
  27 ```
  28
  29 The bootloader shell can be accessed from the serial port:
  30 ```
  31 flterm --speed=9600 /dev/ttyUSB1
  32
  33 LambdaSoC BIOS
  34 (c) Copyright 2007-2020 M-Labs Limited
  35 (c) Copyright 2020 LambdaConcept
  36 Built Mar 26 2020 13:41:04
  37
  38 BIOS CRC passed (c402e7e2)
  39 BIOS>
  40 ```
  41
  42 The `help` command lists available commands.
  43
  44 ## License
  45
  46 LambdaSoC is released under the permissive two-clause BSD license. See LICENSE file for full copyright and license information.
  47
  48 [nmigen-soc]: https://github.com/nmigen/nmigen-soc
  49 [minerva]: https://github.com/lambdaconcept/minerva
  50 [nmigen-boards]: https://github.com/nmigen/nmigen-boards
  51 [sram_soc]: https://github.com/lambdaconcept/lambdasoc/blob/master/examples/sram_soc.py