document useful "add_extension" for HyperRAM PMODs

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index 8220d7b9ebbbec24ad82d59915921872efca0c80..f20f06e1a87b39a5d3eeff50426cd17a2907dfe4 100644 (file)
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -10,6 +10,27 @@
 # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER
 # under EU Grants 871528 and 957073, and Licensed under the LGPLv3+ License
 
+"""
+Usage example when wiring up an external pmod.
+(thanks to daveshah for this tip)
+use platform.add_extension to first define the pins:
+
+    from nmigen.resources.memory import HyperRAMResources
+    hyperram_ios = HyperRAMResources(cs_n="B1",
+                                     dq="D0 D1 D2 D3 D4 D7 D6 D7",
+                                     rwds="B2", rst_n="B3", clk_p="B4",
+                                     attrs=IOStandard("LVCMOS33"))
+    self.platform.add_extension(hyperram_ios)
+    io = self.platform.request("hyperram")
+
+this trick will work with the 1-IC HyperRAM PMOD by Piotr Esden, sold
+by 1bitsquared.  however for the *four* IC HyperRAM PMOD, *four*
+separate and distinct instances are needed, each with a different
+cs_n pin.  on the TODO list for this module: interleave multiple HyperRAM
+cs_n's to give striped (like RAID) memory accesses behind one single
+Wishbone interface.
+"""
+
 
 from nmigen import (Elaboratable, Module, Signal, Record, Cat, Const)
 from nmigen.cli import rtlil