from nmigen.resources.memory import HyperRAMResources
hyperram_ios = HyperRAMResources(cs_n="B1",
dq="D0 D1 D2 D3 D4 D7 D6 D7",
- rwds="B2", rst_n="B3", clk_p="B4",
+ rwds="B2", rst_n="B3", ck_p="B4",
attrs=IOStandard("LVCMOS33"))
self.platform.add_extension(hyperram_ios)
io = self.platform.request("hyperram")
class HyperRAMASICPhy(Elaboratable):
def __init__(self, io):
self.io = io
- self.clk = clk = Signal()
+ self.ck = ck = Signal()
self.cs = cs = Signal()
self.dq_o = dq_o = Signal(8)
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- clk, cs = self.clk, self.cs
+ ck, cs = self.ck, self.cs
dq_o, dq_i, dq_oe = self.dq_o, self.dq_i, self.dq_oe
rwds_o, rwds_oe = self.rwds_o, self.rwds_oe
self.io["rwds_o"].eq(rwds_o),
self.io["csn_o"].eq(~cs),
self.io["csn_oe"].eq(0),
- self.io["clk_o"].eq(clk),
- self.io["clk_oe"].eq(0),
+ self.io["ck_o"].eq(ck),
+ self.io["ck_oe"].eq(0),
self.io["rwds_oe"].eq(~rwds_oe),
]
class HyperRAMPads:
def __init__(self, dw=8):
- self.clk = Signal()
+ self.ck = Signal()
self.cs_n = Signal()
self.dq = Record([("oe", 1), ("o", dw), ("i", dw)])
self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)])
class HyperRAMPHY(Elaboratable):
def __init__(self, pads):
self.pads = pads
- self.clk = pads.clk
+ self.ck = pads.ck
self.cs = Signal()
self.dq_o = pads.dq.o
self.dq_i = pads.dq.i
return m
def ports(self):
- return [self.clk, self.cs, self.dq_o, self.dq_i, self.dq_oe,
+ return [self.ck, self.cs, self.dq_o, self.dq_i, self.dq_oe,
self.rwds_o, self.rwds_oe]
# HyperRAM --------------------------------------------------------------------
This core favors portability and ease of use over performance.
"""
- def __init__(self, *, io, phy_kls, latency=6):
+ def __init__(self, *, io, phy_kls, latency=6, bus=None,
+ features=frozenset()):
super().__init__()
self.io = io
self.phy = phy_kls(io)
self.latency = latency
self.bus = wishbone.Interface(addr_width=21,
- data_width=32, granularity=8)
+ data_width=32, granularity=8,
+ features=features)
mmap = MemoryMap(addr_width=23, data_width=8)
mmap.add_resource(object(), name="hyperram", size=2**23)
self.bus.memory_map = mmap
bus = self.bus
comb, sync = m.d.comb, m.d.sync
- clk = self.phy.clk
+ ck = self.phy.ck
clk_phase = Signal(2)
cs = self.phy.cs
ca = Signal(48)
sync += clk_phase.eq(clk_phase + 1)
with m.Switch(clk_phase):
with m.Case(1):
- sync += clk.eq(cs)
+ sync += ck.eq(cs)
with m.Case(3):
- sync += clk.eq(0)
+ sync += ck.eq(0)
# Data Shift Register (for write and read) ------------------------
dqi = Signal(dw)
if __name__ == '__main__':
layout=[('rwds_o', 1), ('rwds_oe', 1),
('csn_o', 1), ('csn_oe', 1),
- ('clk_o', 1), ('clk_oe', 1)]
+ ('ck_o', 1), ('ck_oe', 1)]
for i in range(8):
layout += [('d%d_o' % i, 1), ('d%d_oe' % i, 1), ('d%d_i' % i, 1)]
io = Record(layout=layout)
yield
def hyperram_gen(dut):
- clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
+ ck = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
cs_n = "--________________________________________________________________------"
dq_oe = "__------------____________________________________________--------______"
dq_o = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
for i in range(3):
yield
if False: # useful for printing out expected vs results
- for i in range(len(clk)):
+ for i in range(len(ck)):
print ("i", i)
- print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
+ print ("ck", c2bool(ck[i]), (yield dut.phy.pads.ck))
print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
print ("dq_oe", c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
print ("dq_o", hex(int(dq_o[2*(i//2):2*(i//2)+2], 16)),
print ("rwds_o", c2bool(rwds_o[i]),
(yield dut.phy.pads.rwds.o))
yield
- for i in range(len(clk)):
- self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
+ for i in range(len(ck)):
+ self.assertEqual(c2bool(ck[i]), (yield dut.phy.pads.ck))
self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
vcd_name="sim.vcd")
- def test_hyperram_read(self):
- def fpga_gen(dut):
- dat = yield from wb_read(dut.bus, 0x1234, 0b1111)
- self.assertEqual(dat, 0xdeadbeef)
- dat = yield from wb_read(dut.bus, 0x1235, 0b1111)
- self.assertEqual(dat, 0xcafefade)
-
- def hyperram_gen(dut):
- clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
- cs_n = "--________________________________________________________________________________"
- dq_oe = "__------------____________________________________________________________________"
- dq_o = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
- dq_i = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
- rwds_oe = "__________________________________________________________________________________"
-
- for i in range(3):
- print ("prep", i)
- yield
- for i in range(len(clk)):
- print ("i", i)
- yield dut.phy.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
- print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
- print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
- yield
- continue
- self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
- self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
- self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
- self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
- (yield dut.phy.pads.dq.o))
- self.assertEqual(c2bool(rwds_oe[i]),
- (yield dut.phy.pads.rwds.oe))
- yield
-
- dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY)
- run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
- vcd_name="rd_sim.vcd")
class TestHyperBusRead(unittest.TestCase):
yield
def hyperram_gen(dut):
- clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
+ ck = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
cs_n = "--________________________________________________________________________________"
dq_oe = "__------------____________________________________________________________________"
dq_o = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
for i in range(3):
print ("prep", i)
yield
- for i in range(len(clk)):
+ for i in range(len(ck)):
print ("i", i)
yield dut.phy.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
- print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
+ print ("ck", c2bool(ck[i]), (yield dut.phy.pads.ck))
print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
print ("dq_oe", c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
print ("dq_o", hex(int(dq_o[2*(i//2):2*(i//2)+2], 16)),
hex((yield dut.phy.pads.dq.o)))
print ("rwds_oe", c2bool(rwds_oe[i]),
(yield dut.phy.pads.rwds.oe))
- self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
+ self.assertEqual(c2bool(ck[i]), (yield dut.phy.pads.ck))
self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
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