8e51dbb117f0f0f68e02e1b0c2c0a066d72a2c90
[libreriscv.git] / conferences / fosdem2024 / fosdem2024_bigint / fosdem2024_bigint.tex
1 % Copyright 2024 Jacob Lifshay
2
3 \documentclass{beamer}
4 \usepackage{beamerthemesplit}
5 \usetheme{default}
6 \usepackage[english]{babel}
7 \usepackage{tikz}
8
9 \title[Fast Big-Integer Arithmetic on SVP64 ...]{
10 Fast Big-Integer Arithmetic on SVP64 at up to 256-bits/cycle and beyond
11 }
12
13 \author{Jacob R. Lifshay}
14
15 \date{FOSDEM 2024}
16
17 \logo{\includegraphics[height=0.5cm]{../../../images/lsoclogo.png}}
18
19 \begin{document}
20
21 \begin{frame}
22 \titlepage
23 \end{frame}
24
25 \begin{frame}[fragile]
26 \frametitle{What is SVP64?}
27 \begin{itemize}
28 \item Vectorization Extension for PowerISA developed by \href{https://libre-soc.org}{Libre-SOC}
29 \pause
30 \item Basically, a way to modify nearly any PowerISA instruction to run it in a HW loop.
31 \pause \\
32 \medskip
33 Simple Example:
34 \begin{semiverbatim}
35 setvl 0, 0, 3, 0, 1, 1 # makes stuff run 3 times
36 sv.add *r3, *r15, r12 # adds 3 times
37 \pause
38 # expands to:
39 add r3, r15, r12 \only<+(1)->{# no * means r12 doesn't increment}
40 add r4, r16, r12 \only<+(1)->{# * means r3 and r15 increment}
41 add r5, r17, r12
42 \end{semiverbatim}
43 \end{itemize}
44 \end{frame}
45
46 \begin{frame}[fragile]
47 \frametitle{Big-Integer Addition on SVP64}
48 How can we use SVP64 to add 192-bit integers?
49 \pause
50 \begin{semiverbatim}
51 setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times
52 addic 0, 0, 0 # clear CA (carry flag)
53 sv.adde *r4, *r4, *r8 # carry-propagating add
54 \pause
55 # expands to:
56 addic 0, 0, 0 # clear CA (carry flag)
57 adde r4, r4, r8
58 adde r5, r5, r9
59 adde r6, r6, r10
60 adde r6, r6, r11
61 \end{semiverbatim}
62 \end{frame}
63
64 \begin{frame}
65 \input{test.dia-tex}
66 \end{frame}
67
68 \end{document}